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author | Tom Rini <trini@ti.com> | 2013-05-31 10:48:03 -0400 |
---|---|---|
committer | Tom Rini <trini@ti.com> | 2013-06-04 16:32:31 -0400 |
commit | 320d9746d3aa8373b86e8f6331bc7c8c8c87fced (patch) | |
tree | b7f97d7ec22b265cbcc426751136d6bbfa7a685b /include/configs/pcm051.h | |
parent | 0ac6db263132113f2ada36628a04e73d3dc2949a (diff) | |
download | u-boot-imx-320d9746d3aa8373b86e8f6331bc7c8c8c87fced.zip u-boot-imx-320d9746d3aa8373b86e8f6331bc7c8c8c87fced.tar.gz u-boot-imx-320d9746d3aa8373b86e8f6331bc7c8c8c87fced.tar.bz2 |
am33xx: Correct NON_SECURE_SRAM_START/END
Prior to Sricharan's cleanup of the boot parameter saving code, we
did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a
problem that the address was pointing to the middle of our running SPL.
Correct to point to the base location of the download image area.
Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being
used. As part of correcting these tests, make use of the fact that
we've always been placing our stack outside of the download image area
(which is fine, once the downloaded image is run, ROM is gone) so
correct the max size test to be the ROM defined top of the download area
to where we link/load at.
Signed-off-by: Tom Rini <trini@ti.com>
---
Changes in v2:
- Fix typo noted by Peter Korsgaard
Diffstat (limited to 'include/configs/pcm051.h')
-rw-r--r-- | include/configs/pcm051.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 478f805..3480302 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -204,8 +204,14 @@ /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (101 * 1024) +/* + * Place the image at the start of the ROM defined image space and leave + * space for SRAM scratch entries (see arch/arm/include/omap_common.h). + * We limit our size to the ROM-defined downloaded image area, and use the + * rest of the space for stack. + */ +#define CONFIG_SPL_TEXT_BASE 0x402F0500 +#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_BSS_START_ADDR 0x80000000 |