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authorWolfgang Denk <wd@pollux.denx.de>2006-04-05 23:55:15 +0200
committerWolfgang Denk <wd@pollux.denx.de>2006-04-05 23:55:15 +0200
commit197b049b8b8a488384f351b988dd15f78830ba4e (patch)
treed059e889505774b875e71335ec06a92078c63cb0 /include/configs/p3p440.h
parentdb28ddb4da7387f4658ae5d032263258e53a1f37 (diff)
parent35118539435d1a6f40eab348a4ac2040f3bd882c (diff)
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Merge with /home/sr/git/u-boot/4xx-sdram
Diffstat (limited to 'include/configs/p3p440.h')
-rw-r--r--include/configs/p3p440.h12
1 files changed, 8 insertions, 4 deletions
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index 831d018..0662544 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
@@ -71,9 +71,10 @@
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/
-#define CFG_SDRAM_TABLE { \
- {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \
- {(64 << 20), 0x00082001}} /* 64MB mode 2, 12x9(4) */
+#define CONFIG_SDRAM_ECC /* enable ECC support */
+#define CFG_SDRAM_TABLE { \
+ {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
+ {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
/*-----------------------------------------------------------------------
* Serial Port
@@ -275,6 +276,9 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
+
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */