rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

1 files changed, 119 insertions, 119 deletions

diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 2df1d9d..5e4d30b 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -43,21 +43,21 @@
 #if defined (CONFIG_P3M750)
 #define CONFIG_750FX			/* 750GL/GX/FX			*/
 #define CONFIG_HIGH_BATS		/* High BATs supported		*/
-#define CFG_BOARD_NAME		"P3M750"
-#define CFG_BUS_HZ		100000000
-#define CFG_BUS_CLK		CFG_BUS_HZ
-#define CFG_TCLK		100000000
+#define CONFIG_SYS_BOARD_NAME		"P3M750"
+#define CONFIG_SYS_BUS_HZ		100000000
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
+#define CONFIG_SYS_TCLK		100000000
 #elif defined (CONFIG_P3M7448)
 #define CONFIG_74xx
-#define CFG_BOARD_NAME		"P3M7448"
-#define CFG_BUS_HZ		133333333
-#define CFG_BUS_CLK		CFG_BUS_HZ
-#define CFG_TCLK		133333333
+#define CONFIG_SYS_BOARD_NAME		"P3M7448"
+#define CONFIG_SYS_BUS_HZ		133333333
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
+#define CONFIG_SYS_TCLK		133333333
 #endif
-#define CFG_GT_DUAL_CPU			/* also for JTAG even with one cpu */
+#define CONFIG_SYS_GT_DUAL_CPU			/* also for JTAG even with one cpu */
 
 /* which initialization functions to call for this board */
-#define CFG_BOARD_ASM_INIT	1
+#define CONFIG_SYS_BOARD_ASM_INIT	1
 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
 #define CONFIG_BOARD_EARLY_INIT_R 1     /* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R      1	/* Call misc_init_r()		*/
@@ -66,42 +66,42 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
 #ifdef CONFIG_P3M750
-#define CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte	*/
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte	*/
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 #if defined (CONFIG_P3M750)
-#define CFG_FLASH_BASE		0xff800000	/* start of flash banks	*/
-#define CFG_BOOT_SIZE		_8M		/* boot flash		*/
+#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of flash banks	*/
+#define CONFIG_SYS_BOOT_SIZE		_8M		/* boot flash		*/
 #elif defined (CONFIG_P3M7448)
-#define CFG_FLASH_BASE		0xff000000	/* start of flash banks	*/
-#define CFG_BOOT_SIZE		_16M		/* boot flash		*/
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of flash banks	*/
+#define CONFIG_SYS_BOOT_SIZE		_16M		/* boot flash		*/
 #endif
-#define CFG_BOOT_SPACE		CFG_FLASH_BASE	/* BOOT_CS0 flash 0    */
-#define CFG_MONITOR_BASE	0xfff00000
-#define CFG_RESET_ADDRESS	0xfff00100
-#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
-#define CFG_MISC_REGION_BASE	0xf0000000
+#define CONFIG_SYS_BOOT_SPACE		CONFIG_SYS_FLASH_BASE	/* BOOT_CS0 flash 0    */
+#define CONFIG_SYS_MONITOR_BASE	0xfff00000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
 
-#define CFG_DFL_GT_REGS		0xf1000000	/* boot time GT_REGS */
-#define CFG_GT_REGS		0xf1000000	/* GT Registers are mapped here */
-#define CFG_INT_SRAM_BASE	0x42000000	/* GT offers 256k internal SRAM */
+#define CONFIG_SYS_DFL_GT_REGS		0xf1000000	/* boot time GT_REGS */
+#define CONFIG_SYS_GT_REGS		0xf1000000	/* GT Registers are mapped here */
+#define CONFIG_SYS_INT_SRAM_BASE	0x42000000	/* GT offers 256k internal SRAM */
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
  /*
- * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
  * To an unused memory region. The stack will remain in cache until RAM
  * is initialized
 */
-#undef	CFG_INIT_RAM_LOCK
-#define CFG_INIT_RAM_ADDR	0x42000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#undef	CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x42000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 
 /*-----------------------------------------------------------------------
@@ -110,15 +110,15 @@
 #define CONFIG_MPSC			/* MV64460 Serial		*/
 #define CONFIG_MPSC_PORT	0
 #define CONFIG_BAUDRATE		115200	/* console baudrate		*/
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 /*-----------------------------------------------------------------------
  * Ethernet
  *----------------------------------------------------------------------*/
 /* Change the default ethernet port, use this define (options: 0, 1, 2) */
-#define CFG_ETH_PORT		ETH_0
+#define CONFIG_SYS_ETH_PORT		ETH_0
 #define CONFIG_NET_MULTI
 #define MV_ETH_DEVS		2
 #define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
@@ -127,15 +127,15 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI			/* The flash is CFI compatible		*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible		*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver		*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 #if defined (CONFIG_P3M750)
@@ -144,7 +144,7 @@
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* two sectors (2 devices parallel	*/
 #endif
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -154,12 +154,12 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CFG_I2C_SPEED		100000		/* I2C speed default	*/
+#define CONFIG_SYS_I2C_SPEED		100000		/* I2C speed default	*/
 
 /* I2C RTC */
 #define CONFIG_RTC_M41T11	1
-#define CFG_I2C_RTC_ADDR	0x68
-#define CFG_M41T11_BASE_YEAR	1900	/* play along with linux	*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with linux	*/
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -176,27 +176,27 @@
 #endif /* CONFIG_PCI */
 
 /* PCI MEMORY MAP section */
-#define CFG_PCI0_MEM_BASE	0x80000000
-#define CFG_PCI0_MEM_SIZE	_128M
-#define CFG_PCI1_MEM_BASE	0x88000000
-#define CFG_PCI1_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
 
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
-#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
 
 /* PCI I/O MAP section */
-#define CFG_PCI0_IO_BASE	0xfa000000
-#define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
 
-#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
-#define CFG_PCI0_IO_SPACE_PCI	0x00000000
-#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
-#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
 
-#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
-#define CFG_PCI_IDSEL 0x30
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI_IDSEL 0x30
 
 #undef	CONFIG_BOOTARGS
 #define	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
@@ -285,26 +285,26 @@
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x08000000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x08000000	/* default load address */
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
@@ -317,9 +317,9 @@
  *----------------------------------------------------------------------*/
 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
 #if defined (CONFIG_P3M750)
-#define CFG_BOOT_PAR		0x8FDFF87F	/* 16 bit flash, disable burst*/
+#define CONFIG_SYS_BOOT_PAR		0x8FDFF87F	/* 16 bit flash, disable burst*/
 #elif defined (CONFIG_P3M7448)
-#define CFG_BOOT_PAR		0x8FEFFFFF	/* 32 bit flash, burst enabled */
+#define CONFIG_SYS_BOOT_PAR		0x8FEFFFFF	/* 32 bit flash, burst enabled */
 #endif
 
 /*
@@ -356,11 +356,11 @@
  * MPP[30]	Module reset		GPIO	OUT	Board reset
  * MPP[31]	PCI EReady		GPIO	IN	Connected to P12
  */
-#define CFG_MPP_CONTROL_0	0x00303022
-#define CFG_MPP_CONTROL_1	0x00000000
-#define CFG_MPP_CONTROL_2	0x00004000
-#define CFG_MPP_CONTROL_3	0x00000004
-#define CFG_GPP_LEVEL_CONTROL	0x280730D0
+#define CONFIG_SYS_MPP_CONTROL_0	0x00303022
+#define CONFIG_SYS_MPP_CONTROL_1	0x00000000
+#define CONFIG_SYS_MPP_CONTROL_2	0x00004000
+#define CONFIG_SYS_MPP_CONTROL_3	0x00000004
+#define CONFIG_SYS_GPP_LEVEL_CONTROL	0x280730D0
 
 /*----------------------------------------------------------------------
  * Initial BAT mappings
@@ -371,75 +371,75 @@
  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
  */
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 
 /* init ram */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 
 /* PCI0, PCI1 in one BAT */
-#define CFG_IBAT2L BATL_NO_ACCESS
-#define CFG_IBAT2U CFG_DBAT2U
-#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* GT regs, bootrom, all the devices, PCI I/O */
-#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
-#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT4U CFG_IBAT4U
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
 
 /* set rest out of range for Linux !!!!!!!!!!! */
 
 /* IBAT5 and DBAT5 */
-#define CFG_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT5U CFG_IBAT5U
+#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
 
 /* IBAT6 and DBAT6 */
-#define CFG_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U CFG_IBAT6U
+#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
 
 /* IBAT7 and DBAT7 */
-#define CFG_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT7U CFG_IBAT7U
+#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
-#define CFG_VXWORKS_MAC_PTR	0x42010000 /* use some memory in SRAM that's not used!!! */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x42010000 /* use some memory in SRAM that's not used!!! */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
  * L2CR setup -- make sure this is right for your board!
  * look in include/mpc74xx.h for the defines used here
  */
-#define CFG_L2
+#define CONFIG_SYS_L2
 
 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
 #define L2_INIT 0