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authorKumar Gala <galak@kernel.crashing.org>2009-09-15 22:21:58 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-09-24 12:04:57 -0500
commit202d94875c98b7b573f136c4f353609758ed9733 (patch)
treee0af514570c712830620de7fb014415504da698c /include/configs/omap730.h
parent30d7aae7e82dacf9ae2983fbbf3567515266968b (diff)
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ppc/85xx: Fix LCRR_CLKDIV defines
For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'include/configs/omap730.h')
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