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authorMarkus Klotzbuecher <mk@denx.de>2007-05-29 16:37:57 +0200
committerMarkus Klotzbuecher <mk@pollux.denx.de>2007-05-29 16:37:57 +0200
commit51d8e813222fa3063d423220f6ff1146df58a471 (patch)
treea4951077af841bd87a90854b7fb390d12e37b851 /include/configs/o2dnt.h
parent3a619dd7bed03e8b4d22a3911f90fd12af5376c2 (diff)
parent19bf91f9628f80a55d4f171df71041574882b3d6 (diff)
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Merge git://www.denx.de/git/u-boot into 2007_05_15-testing
Diffstat (limited to 'include/configs/o2dnt.h')
-rw-r--r--include/configs/o2dnt.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 5c05a74..63d0da7 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -137,17 +137,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
#endif
@@ -276,7 +276,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
/*
* For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
*/