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| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2012-03-22 12:00:31 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-04-16 14:53:58 +0200 |
| commit | 148241053123f3c2388d755807438fbe44dd2139 (patch) | |
| tree | 9fe038dbbe9cec28b1f9e6af030d9ee719eb2ac6 /include/configs/mx6qsabrelite.h | |
| parent | 607dfdf568baa506dc4ff33a38be3478820648fd (diff) | |
| download | u-boot-imx-148241053123f3c2388d755807438fbe44dd2139.zip u-boot-imx-148241053123f3c2388d755807438fbe44dd2139.tar.gz u-boot-imx-148241053123f3c2388d755807438fbe44dd2139.tar.bz2 | |
MX53: DDR: Fix ZQHWCTRL field TZQ_CS
Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'include/configs/mx6qsabrelite.h')
0 files changed, 0 insertions, 0 deletions