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authorJason Chen <b02280@freescale.com>2011-03-31 15:30:23 +0800
committerJason Chen <b02280@freescale.com>2011-03-31 15:30:23 +0800
commit0f165488b255c8243284e1fbf6ebd74f2795dd0a (patch)
tree25e2fe1d169f70a87336ce9ebc6d9f5645c6b0af /include/configs/mx53_evk.h
parent068bed0069dfe66bf01cc72fc4e41a32b2cb94d4 (diff)
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ENGR00141363: change mx53 uart clk parent to pll2
Change all mx53 platform uart clk default parent to pll2. MX53 SMD board need support LVDS and HDMI at the same time, they may use the same clock parent-pll4, so kernel need change ipu di clock parent to pll3, after that, uart clock parent need change to pll2 to avoid console mess. Signed-off-by: Jason Chen <b02280@freescale.com>
Diffstat (limited to 'include/configs/mx53_evk.h')
-rw-r--r--include/configs/mx53_evk.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/configs/mx53_evk.h b/include/configs/mx53_evk.h
index e2458a0..4ddc10d 100644
--- a/include/configs/mx53_evk.h
+++ b/include/configs/mx53_evk.h
@@ -39,10 +39,10 @@
#define CONFIG_ARCH_MMU
#define CONFIG_MX53_HCLK_FREQ 24000000
-#define CONFIG_SYS_PLL2_FREQ 600
-#define CONFIG_SYS_AHB_PODF 4
-#define CONFIG_SYS_AXIA_PODF 1
-#define CONFIG_SYS_AXIB_PODF 2
+#define CONFIG_SYS_PLL2_FREQ 400
+#define CONFIG_SYS_AHB_PODF 2
+#define CONFIG_SYS_AXIA_PODF 0
+#define CONFIG_SYS_AXIB_PODF 1
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO