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authorStefano Babic <sbabic@denx.de>2010-08-23 20:41:19 +0200
committerStefano Babic <sbabic@denx.de>2010-09-30 14:42:13 +0200
commit9f481e95baaca2a5a739f930c16b1cc485b0c1f3 (patch)
treef569b9da23b356a660168a2f2dbcc2708eff6fa0 /include/configs/mx31pdk.h
parent4d0e49d33639394d25a60a4e2d73e99634348af7 (diff)
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MXC: Correct SPI_CPOL setting in SPI driver
The handling of the SPI_CPOL bit inside the SPI driver was wrong. As reported by the manual, the meaning of the SSPOL inside the configuration register is the same as reported by SPI specification (0 if low in idle, 1 is high on idle). The driver inverts this logic. Because this patch sets the logic as specified, it is required to clear the CPOL bit in the configuration file to adapt to the correct logic. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: David Jander <david.jander@protonic.nl>
Diffstat (limited to 'include/configs/mx31pdk.h')
-rw-r--r--include/configs/mx31pdk.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 0414cc3..4b4fb1a 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -67,13 +67,13 @@
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 2
#define CONFIG_FSL_PMIC_CLK 1000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
/* allow to overwrite serial and ethaddr */