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| author | Martha M Stan <mmarx@silicontkx.com> | 2009-09-21 14:08:00 -0400 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-09-25 00:45:38 +0200 |
| commit | a5aa3998ab6408a6ac738a3ce8005e647b9465f8 (patch) | |
| tree | 16bf1fd5cb42788a63ecf61531dc45e9f725723c /include/configs/mpc5121ads.h | |
| parent | 054197ba8ee5ef1e41694df58531b6e53ec43f2d (diff) | |
| download | u-boot-imx-a5aa3998ab6408a6ac738a3ce8005e647b9465f8.zip u-boot-imx-a5aa3998ab6408a6ac738a3ce8005e647b9465f8.tar.gz u-boot-imx-a5aa3998ab6408a6ac738a3ce8005e647b9465f8.tar.bz2 | |
Add Elpida Memory Configuration to mpc5121ads Boards
Signed-off-by: Martha M Stan <mmarx@silicontkx.com>
Minor coding style cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include/configs/mpc5121ads.h')
| -rw-r--r-- | include/configs/mpc5121ads.h | 35 |
1 files changed, 33 insertions, 2 deletions
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 0c871c9..ebc518c 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -141,14 +141,45 @@ #endif #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E +#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00 +#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 +#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 + #define CONFIG_SYS_DDRCMD_NOP 0x01380000 #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 #define CONFIG_SYS_DDRCMD_EM2 0x01020000 #define CONFIG_SYS_DDRCMD_EM3 0x01030000 #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 + +#define DDRCMD_EMR_OCD(pr, ohm) ( \ + (1 << 24) | /* MDDRC Command Request */ \ + (1 << 16) | /* MODE Reg BA[2:0] */ \ + (0 << 12) | /* Outputs 0=Enabled */ \ + (0 << 11) | /* RDQS */ \ + (1 << 10) | /* DQS# */ \ + (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ + /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ + ((ohm & 0x2) << 5)| /* Rtt1 */ \ + (0 << 3) | /* additive posted CAS# */ \ + ((ohm & 0x1) << 2)| /* Rtt0 */ \ + (0 << 0) | /* Output Drive Strength */ \ + (0 << 0)) /* DLL Enable 0=Normal */ + +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0) +#define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) + +#define DDRCMD_MODE_REG(cas, wr) ( \ + (1 << 24) | /* MDDRC Command Request */ \ + (0 << 16) | /* MODE Reg BA[2:0] */ \ + ((wr-1) << 9)| /* Write Recovery */ \ + (cas << 4) | /* CAS */ \ + (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ + (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ + +#define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) +#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) +#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 |