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authorHaiying Wang <Haiying.Wang@freescale.com>2008-10-03 12:37:26 -0400
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:05 +0200
commit1f293b417ac6ab8e317ca2b770377ca93edf2370 (patch)
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parentc9ffd839b1ada502c86f88edaf1534426b6688ce (diff)
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Add debug information for DDR controller registers
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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