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| author | Wolfgang Grandegger <wg@denx.de> | 2009-10-23 12:03:13 +0200 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2009-10-31 12:13:28 +0100 |
| commit | c28d3bbe963f4c57937d6fdc1dd63cd3562c147c (patch) | |
| tree | 7bb2e6539685e5a72a222bb0a4364409d5d96aa7 /include/configs/lwmon5.h | |
| parent | f2b4bc04d6aed6be712d236dab48ac4c4da22cbf (diff) | |
| download | u-boot-imx-c28d3bbe963f4c57937d6fdc1dd63cd3562c147c.zip u-boot-imx-c28d3bbe963f4c57937d6fdc1dd63cd3562c147c.tar.gz u-boot-imx-c28d3bbe963f4c57937d6fdc1dd63cd3562c147c.tar.bz2 | |
video: mb862xx: improve board-specific Lime configuration
To avoid board-specific code accessing the mb862xx registers directly,
the public function mb862xx_probe() has been introduced. Furthermore,
the "Change of Clock Frequency" and "Set Memory I/F Mode" registers
are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR,
respectively. The BSPs for the socrates and lwmon5 boards have been
adapted accordingly.
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Diffstat (limited to 'include/configs/lwmon5.h')
| -rw-r--r-- | include/configs/lwmon5.h | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 777a4d6..67434f5 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -495,8 +495,6 @@ /*----------------------------------------------------------------------- * Graphics (Fujitsu Lime) *----------------------------------------------------------------------*/ -/* SDRAM Clock frequency adjustment register */ -#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 /* Lime Clock frequency is to set 100MHz */ #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 #if 0 @@ -504,15 +502,15 @@ #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 #endif -/* SDRAM Parameter register */ -#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars and pixel flare on display when 133MHz was configured. According to SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ -#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F3 +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ #else -#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F2 +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ #endif /*----------------------------------------------------------------------- |