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author | Wolfgang Denk <wd@denx.de> | 2009-10-31 16:13:18 +0100 |
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committer | Wolfgang Denk <wd@denx.de> | 2009-10-31 16:13:18 +0100 |
commit | d793b6bb1e37ccaba702bac088bfc0d0e91ac734 (patch) | |
tree | 9367f4cf04b7e978ad39ae22453963ab03056c19 /include/configs/lwmon5.h | |
parent | 08ea550eef310e9d59d83f3cfd57a902373bf17f (diff) | |
parent | 229b6dce675c729ee0ea2d7b61fbcda89b23b6b8 (diff) | |
download | u-boot-imx-d793b6bb1e37ccaba702bac088bfc0d0e91ac734.zip u-boot-imx-d793b6bb1e37ccaba702bac088bfc0d0e91ac734.tar.gz u-boot-imx-d793b6bb1e37ccaba702bac088bfc0d0e91ac734.tar.bz2 |
Merge branch 'next' of git://git.denx.de/u-boot-video into next
Diffstat (limited to 'include/configs/lwmon5.h')
-rw-r--r-- | include/configs/lwmon5.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 777a4d6..011dd5c 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -344,10 +344,12 @@ /* Video console */ #define CONFIG_VIDEO #define CONFIG_VIDEO_MB862xx +#define CONFIG_VIDEO_MB862xx_ACCEL #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO #define CONFIG_CONSOLE_EXTRA_INFO #define VIDEO_FB_16BPP_PIXEL_SWAP +#define VIDEO_FB_16BPP_WORD_SWAP #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_SW_CURSOR @@ -495,8 +497,6 @@ /*----------------------------------------------------------------------- * Graphics (Fujitsu Lime) *----------------------------------------------------------------------*/ -/* SDRAM Clock frequency adjustment register */ -#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 /* Lime Clock frequency is to set 100MHz */ #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 #if 0 @@ -504,15 +504,15 @@ #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 #endif -/* SDRAM Parameter register */ -#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars and pixel flare on display when 133MHz was configured. According to SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ -#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F3 +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ #else -#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F2 +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ #endif /*----------------------------------------------------------------------- |