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| author | Stefan Roese <sr@denx.de> | 2008-01-09 10:28:20 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-01-09 10:28:20 +0100 |
| commit | 8f24e0637ae113500d8bd60d80d57afcc0aa8bde (patch) | |
| tree | 4f17b423e33303a05b883cfede86c1b42714283b /include/configs/lwmon5.h | |
| parent | 1754f50b710194f886b6f2831803d8960171a14d (diff) | |
| download | u-boot-imx-8f24e0637ae113500d8bd60d80d57afcc0aa8bde.zip u-boot-imx-8f24e0637ae113500d8bd60d80d57afcc0aa8bde.tar.gz u-boot-imx-8f24e0637ae113500d8bd60d80d57afcc0aa8bde.tar.bz2 | |
ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymore
This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/lwmon5.h')
| -rw-r--r-- | include/configs/lwmon5.h | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 5210024..0bf536b 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -71,15 +71,20 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer *----------------------------------------------------------------------*/ -/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ -#define CFG_OCM_DATA_ADDR CFG_OCM_BASE - +/* + * On LWMON5 we use D-cache as init-ram and stack pointer. We also move + * the POST_WORD from OCM to a 440EPx register that preserves it's + * content during reset (GPT0_COM6). This way we reserve the OCM (16k) + * for logbuffer only. + */ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (4 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) + /* unused GPT0 COMP reg */ /*----------------------------------------------------------------------- * Serial Port |