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author | Wolfgang Denk <wd@denx.de> | 2008-01-09 21:34:46 +0100 |
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committer | Wolfgang Denk <wd@denx.de> | 2008-01-09 21:34:46 +0100 |
commit | 3b93020d74630f0574cbd26d200a82c00dd11eaa (patch) | |
tree | fdf53ce4da01d337ceb71cadf496a9fc8d2fb62c /include/configs/lwmon5.h | |
parent | c83d7ca4dadd44ae430235077f63b64a11f36f6e (diff) | |
parent | 6007f3251c0967adc13f2ed8be1b924ddc30124d (diff) | |
download | u-boot-imx-3b93020d74630f0574cbd26d200a82c00dd11eaa.zip u-boot-imx-3b93020d74630f0574cbd26d200a82c00dd11eaa.tar.gz u-boot-imx-3b93020d74630f0574cbd26d200a82c00dd11eaa.tar.bz2 |
Merge branch 'master' of /home/wd/git/u-boot/master/
Diffstat (limited to 'include/configs/lwmon5.h')
-rw-r--r-- | include/configs/lwmon5.h | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 5210024..0bf536b 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -71,15 +71,20 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer *----------------------------------------------------------------------*/ -/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ -#define CFG_OCM_DATA_ADDR CFG_OCM_BASE - +/* + * On LWMON5 we use D-cache as init-ram and stack pointer. We also move + * the POST_WORD from OCM to a 440EPx register that preserves it's + * content during reset (GPT0_COM6). This way we reserve the OCM (16k) + * for logbuffer only. + */ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (4 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) + /* unused GPT0 COMP reg */ /*----------------------------------------------------------------------- * Serial Port |