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authorYork Sun <yorksun@freescale.com>2014-09-08 12:20:01 -0700
committerYork Sun <yorksun@freescale.com>2014-09-25 08:36:19 -0700
commit8bfa301b0a30f57888d2117767b23f168760bc40 (patch)
tree623535f20c95354efb54eb2313393bd3499cbfe4 /include/configs/ls2085a_common.h
parent40f8dec54d7803975aed1c88327002c95ea99908 (diff)
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ARMv8/ls2085a: Enable secondary cores
Spin table is at the very beginning of boot code. Each core has an individual release address within the spin table, the ft_cpu_setup fn updates the "cpu-release-addr" property of each cpu node with the corresponding release address. Also fix CPU_RELEASE_ADDR to point to secondary_boot_func. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Diffstat (limited to 'include/configs/ls2085a_common.h')
-rw-r--r--include/configs/ls2085a_common.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 5ac7623..1455f88 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -47,15 +47,17 @@
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
-/* SMP Definitions */
-#define CPU_RELEASE_ADDR CONFIG_SYS_INIT_SP_ADDR
-
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
/*
@@ -241,6 +243,7 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+#define CONFIG_ARCH_EARLY_INIT_R
/* Physical Memory Map */
/* fixme: these need to be checked against the board */