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| author | Shaohui Xie <Shaohui.Xie@nxp.com> | 2016-09-07 17:56:14 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:11:10 -0700 |
| commit | 126fe70d7746d7e60a6331391cab6713368b78dc (patch) | |
| tree | 493e24425877158f124d576bea9d29bc365c3385 /include/configs/ls1046a_common.h | |
| parent | dd02936f81de477680f27af244fd2085ce460152 (diff) | |
| download | u-boot-imx-126fe70d7746d7e60a6331391cab6713368b78dc.zip u-boot-imx-126fe70d7746d7e60a6331391cab6713368b78dc.tar.gz u-boot-imx-126fe70d7746d7e60a6331391cab6713368b78dc.tar.bz2 | |
armv8: ls1046aqds: Add LS1046AQDS board support
LS1046AQDS Specification:
-------------------------
Memory subsystem:
* 8GByte DDR4 SDRAM (64bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 64 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* Two XFI 10G ports
* Two SGMII ports
* Two RGMII ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/configs/ls1046a_common.h')
| -rw-r--r-- | include/configs/ls1046a_common.h | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 9ee29b4..5856de8 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -80,6 +80,36 @@ #define CONFIG_SYS_MONITOR_LEN 0xa0000 #endif +/* NAND SPL */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PBL_PAD +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT + +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */ +#define CONFIG_SPL_STACK 0x1001f000 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SYS_MONITOR_LEN 0xa0000 +#endif + /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC @@ -117,13 +147,19 @@ */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#else +#elif defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x40300000 #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 1000000 #define CONFIG_ENV_SPI_MODE 0x03 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |