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| author | York Sun <yorksun@freescale.com> | 2014-09-11 13:32:07 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-25 09:12:12 -0700 |
| commit | c7eae7fcb11bc7dab519fca8d8902f1fbc5c3c76 (patch) | |
| tree | 1a521d509a9752c0f279416c7d54c98c1d854068 /include/configs/ls1021aqds.h | |
| parent | f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb (diff) | |
| download | u-boot-imx-c7eae7fcb11bc7dab519fca8d8902f1fbc5c3c76.zip u-boot-imx-c7eae7fcb11bc7dab519fca8d8902f1fbc5c3c76.tar.gz u-boot-imx-c7eae7fcb11bc7dab519fca8d8902f1fbc5c3c76.tar.bz2 | |
board/ls1021aqds: Add DDR4 support
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Diffstat (limited to 'include/configs/ls1021aqds.h')
| -rw-r--r-- | include/configs/ls1021aqds.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 657e3b6..bb47813 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -49,10 +49,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#define CONFIG_SYS_DDR_RAW_TIMING +#endif #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 |