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| author | Stefan Roese <sr@denx.de> | 2008-06-02 17:13:55 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-06-03 20:22:03 +0200 |
| commit | ec724f883ee3f3925e6c55027e8ffa70ada83303 (patch) | |
| tree | fe01db2e9f65d2743d237714fae0526bd45bfc45 /include/configs/kilauea.h | |
| parent | 17ceb069b85fbb9269c4dc09b2c237f88334c5ba (diff) | |
| download | u-boot-imx-ec724f883ee3f3925e6c55027e8ffa70ada83303.zip u-boot-imx-ec724f883ee3f3925e6c55027e8ffa70ada83303.tar.gz u-boot-imx-ec724f883ee3f3925e6c55027e8ffa70ada83303.tar.bz2 | |
ppc4xx: Change Kilauea to use the common DDR2 init function
This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.
Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/kilauea.h')
| -rw-r--r-- | include/configs/kilauea.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 035a40e..205577f 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -170,9 +170,9 @@ * This NAND U-Boot (NUB) is a special U-Boot version which can be started * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 + * On 405EX the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from location 0xfffff000...0xffffffff the + * NAND controller cannot be accessed since it is attached to CS0 too. */ #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ @@ -511,7 +511,7 @@ /* Memory Bank 2 (FPGA) initialization */ #define CFG_EBC_PB2AP 0x9400C800 -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB2CR (CFG_FPGA_BASE | 0x18000) #define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */ |