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| author | Dirk Eibach <eibach@gdsys.de> | 2011-10-04 11:13:55 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2011-10-12 11:50:42 +0200 |
| commit | 15cc385e681c47851f32fc25c1cd95ab8efbd50c (patch) | |
| tree | 92c9ca616b3c4bf94a97a8ca10abd9ce4607e126 /include/configs/intip.h | |
| parent | 97ca7b3b8e1d1637d95ed249aa233e669087d701 (diff) | |
| download | u-boot-imx-15cc385e681c47851f32fc25c1cd95ab8efbd50c.zip u-boot-imx-15cc385e681c47851f32fc25c1cd95ab8efbd50c.tar.gz u-boot-imx-15cc385e681c47851f32fc25c1cd95ab8efbd50c.tar.bz2 | |
ppc4xx: Change DDR2 CL from 4 to 5 for intip
Some intip boards don't seem to run stable with CL4, datasheets suggest that
CL5 is the safe value.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/intip.h')
| -rw-r--r-- | include/configs/intip.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/intip.h b/include/configs/intip.h index 931a43f..92b65af 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -37,10 +37,10 @@ #define CONFIG_460EX 1 /* Specific PPC460EX */ #ifdef CONFIG_DEVCONCENTER #define CONFIG_HOSTNAME devconcenter -#define CONFIG_IDENT_STRING " devconcenter 0.03" +#define CONFIG_IDENT_STRING " devconcenter 0.05" #else #define CONFIG_HOSTNAME intip -#define CONFIG_IDENT_STRING " intip 0.03" +#define CONFIG_IDENT_STRING " intip 0.05" #endif #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ @@ -200,13 +200,13 @@ #define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000 #define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000 #define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002 -#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542 +#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552 #define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400 #define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000 #define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000 #define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000 #define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000 -#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442 +#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452 #define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382 #define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002 #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000 @@ -216,11 +216,11 @@ #define CONFIG_SYS_SDRAM0_RDCC 0x40000000 #define CONFIG_SYS_SDRAM0_DLCR 0x00000000 #define CONFIG_SYS_SDRAM0_CLKTR 0x40000000 -#define CONFIG_SYS_SDRAM0_WRDTR 0x84000823 +#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823 #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000 #define CONFIG_SYS_SDRAM0_SDTR2 0x32204232 #define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15 -#define CONFIG_SYS_SDRAM0_MMODE 0x00000442 +#define CONFIG_SYS_SDRAM0_MMODE 0x00000452 #define CONFIG_SYS_SDRAM0_MEMODE 0x00000002 #define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */ |