avr32: Add simple paging support

Use the MMU hardware to set up 1:1 mappings between physical and virtual
addresses. This allows us to bypass the cache when accessing the flash
without having to do any physical-to-virtual address mapping in the CFI
driver.

The virtual memory mappings are defined at compile time through a sorted
array of virtual memory range objects. When a TLB miss exception
happens, the exception handler does a binary search through the array
until it finds a matching entry and loads it into the TLB. The u-boot
image itself is covered by a fixed TLB entry which is never replaced.

This makes the 'saveenv' command work again on ATNGW100 and other boards
using the CFI driver, hopefully without breaking any rules.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h
index 0c70af5..8ca04ea 100644
--- a/include/configs/hammerhead.h
+++ b/include/configs/hammerhead.h
@@ -47,6 +47,9 @@
 #define CONFIG_SYS_CLKDIV_PBA			2
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>