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| author | Christian Riesch <christian.riesch@omicron.at> | 2012-02-02 00:44:39 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-12 10:11:33 +0100 |
| commit | b67d8816fd62f0a379caa16846381b5a4e4de398 (patch) | |
| tree | 26c11e8d3187e2081290feb7d9fa6955aafb1973 /include/configs/enbw_cmc.h | |
| parent | da104e04ecc30b90fdc121737f220f0d9c252196 (diff) | |
| download | u-boot-imx-b67d8816fd62f0a379caa16846381b5a4e4de398.zip u-boot-imx-b67d8816fd62f0a379caa16846381b5a4e4de398.tar.gz u-boot-imx-b67d8816fd62f0a379caa16846381b5a4e4de398.tar.bz2 | |
arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
The V bit of the c1 register of CP15 should not be cleared on DA850
SoCs since they have no valid memory at 0x00000000. This patch
introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
that allows setting the correct value for the V bit.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Reported-by: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'include/configs/enbw_cmc.h')
| -rw-r--r-- | include/configs/enbw_cmc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index 9842179..053cfa4 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -40,6 +40,7 @@ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE |