Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

1 files changed, 133 insertions, 133 deletions

diff --git a/include/configs/debris.h b/include/configs/debris.h
index 7667e5e..4d65f6a 100644
--- a/include/configs/debris.h
+++ b/include/configs/debris.h
@@ -76,7 +76,7 @@
 #define CONFIG_SERVERIP	192.168.0.1
 
 /* autoload */
-#undef CFG_AUTOLOAD
+#undef CONFIG_SYS_AUTOLOAD
 
 /* rootpath */
 #define CONFIG_ROOTPATH /tftpboot/target
@@ -156,14 +156,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -174,7 +174,7 @@
 
 #define CONFIG_NET_MULTI		/* Multi ethernet cards support */
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100  */
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100  */
 #define CONFIG_EEPRO100_SROM_WRITE
 
 #define PCI_ENET0_IOADDR	0x80000000
@@ -184,49 +184,49 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x20000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x20000000
 #define CONFIG_VERY_BIG_RAM
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00040000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		0x00040000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_END	0x10000
+#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00040000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00040000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE	128
+/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_END      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 #endif
 
-#define CFG_FLASH_BASE		0x7C000000
-#define CFG_FLASH_SIZE		(16*1024*1024)	/* debris has tiny eeprom	*/
+#define CONFIG_SYS_FLASH_BASE		0x7C000000
+#define CONFIG_SYS_FLASH_SIZE		(16*1024*1024)	/* debris has tiny eeprom	*/
 
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
 
-#define CFG_EUMB_ADDR		0xFC000000
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
 
-#define CFG_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x01000000
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
 #define FLASH_BASE0_PRELIM	0x7C000000	/* debris flash		*/
 
 /*
@@ -251,20 +251,20 @@
 #define MTDPARTS_DEFAULT	"mtdparts=debris-0:-(jffs2)"
 */
 
-#define CFG_ENV_IS_IN_NVRAM      1
+#define CONFIG_ENV_IS_IN_NVRAM      1
 #define CONFIG_ENV_OVERWRITE     1
-#define CFG_NVRAM_ACCESS_ROUTINE 1
-#define CFG_ENV_ADDR		0xFF000000 /* right at the start of NVRAM  */
-#define CFG_ENV_SIZE		0x400	/* Size of the Environment - 8K	   */
-#define CFG_ENV_OFFSET		0	/* starting right at the beginning */
+#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
+#define CONFIG_ENV_ADDR		0xFF000000 /* right at the start of NVRAM  */
+#define CONFIG_ENV_SIZE		0x400	/* Size of the Environment - 8K	   */
+#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning */
 
-#define CFG_NVRAM_BASE_ADDR	0xff000000
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xff000000
 
 /*
- * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS =
+ * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
  * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
  */
-#define CFG_NVRAM_VXWORKS_OFFS	0x6900
+#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900
 
 /*
  * select i2c support configuration
@@ -275,8 +275,8 @@
  */
 #define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
 #undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 #ifdef CONFIG_SOFT_I2C
 #error "Soft I2C is not configured properly.  Please review!"
@@ -291,13 +291,13 @@
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 #endif /* CONFIG_SOFT_I2C */
 
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
@@ -306,17 +306,17 @@
 /*
  * NS16550 Configuration
  */
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		7372800
+#define CONFIG_SYS_NS16550_CLK		7372800
 
-#define CFG_NS16550_COM1	0xFF080000
-#define CFG_NS16550_COM2	(CFG_NS16550_COM1 + 8)
-#define CFG_NS16550_COM3	(CFG_NS16550_COM1 + 16)
-#define CFG_NS16550_COM4	(CFG_NS16550_COM1 + 24)
+#define CONFIG_SYS_NS16550_COM1	0xFF080000
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_NS16550_COM1 + 8)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_NS16550_COM1 + 16)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_NS16550_COM1 + 24)
 
 /*
  * Low Level Configuration Settings
@@ -327,32 +327,32 @@
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
 
-#define CFG_DLL_EXTEND		0x00
-#define CFG_PCI_HOLD_DEL	0x20
+#define CONFIG_SYS_DLL_EXTEND		0x00
+#define CONFIG_SYS_PCI_HOLD_DEL	0x20
 
-#define CFG_ROMNAL	15	/* rom/flash next access time */
-#define CFG_ROMFAL	31	/* rom/flash access time */
+#define CONFIG_SYS_ROMNAL	15	/* rom/flash next access time */
+#define CONFIG_SYS_ROMFAL	31	/* rom/flash access time */
 
-#define CFG_REFINT	430	/* # of clocks between CBR refresh cycles */
+#define CONFIG_SYS_REFINT	430	/* # of clocks between CBR refresh cycles */
 
-#define CFG_DBUS_SIZE2	1	/* set for 8-bit RCS1, clear for 32,64 */
+#define CONFIG_SYS_DBUS_SIZE2	1	/* set for 8-bit RCS1, clear for 32,64 */
 
 /* the following are for SDRAM only*/
-#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC	8	/* Refresh to activate interval		*/
-#define CFG_RDLAT	4	/* data latency from read command	*/
-#define CFG_PRETOACT	3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE	5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		3	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC	8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT	4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT	3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE	5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
 #if 0
-#define CFG_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
 #endif
 
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM 1
-#define CFG_REGDIMM 0
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM 1
+#define CONFIG_SYS_REGDIMM 0
 
 
 /* memory bank settings*/
@@ -362,93 +362,93 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(0x4000000 - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x04000000
-#define CFG_BANK1_END		(0x8000000 - 1)
-#define CFG_BANK1_ENABLE	1
-#define CFG_BANK2_START		0x3ff00000
-#define CFG_BANK2_END		0x3fffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x3ff00000
-#define CFG_BANK3_END		0x3fffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(0x4000000 - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x04000000
+#define CONFIG_SYS_BANK1_END		(0x8000000 - 1)
+#define CONFIG_SYS_BANK1_ENABLE	1
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
 /*
  * Memory bank enable bitmask, specifying which of the banks defined above
  are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
-#define CFG_ODCR		0x75	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0x75	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 1GB (no backing mem) */
 #if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
 #else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 #endif
 
 /* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif