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| author | wdenk <wdenk> | 2004-01-02 14:00:00 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-01-02 14:00:00 +0000 |
| commit | d4ca31c40e8888b36635967522ec7ea03fd7e70b (patch) | |
| tree | 126385a917df4665532dc33cff5fee2977e8fc0e /include/configs/dbau1x00.h | |
| parent | c18960049f8ea9b0a8ad0a05c93e23fbab025da0 (diff) | |
| download | u-boot-imx-d4ca31c40e8888b36635967522ec7ea03fd7e70b.zip u-boot-imx-d4ca31c40e8888b36635967522ec7ea03fd7e70b.tar.gz u-boot-imx-d4ca31c40e8888b36635967522ec7ea03fd7e70b.tar.bz2 | |
* Cleanup lowboot code for MPC5200
* Minor code cleanup (coding style)
* Patch by Reinhard Meyer, 30 Dec 2003:
- cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
- added CONFIG_PHY_ADDR to include/configs/IceCube.h,
- turned debug print of PHY registers into a function (called in two places)
- added support for EMK MPC5200 based modules
* Fix MPC8xx PLPRCR_MFD_SHIFT typo
* Add support for TQM866M modules
* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)
* Fix a few compiler warnings
Diffstat (limited to 'include/configs/dbau1x00.h')
| -rw-r--r-- | include/configs/dbau1x00.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 6f647f2..d78b727 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -30,24 +30,24 @@ #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_DBAU1X00 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_AU1X00 1 /* alchemy series cpu */ #ifdef CONFIG_DBAU1000 /* Also known as Merlot */ -#define CONFIG_AU1000 1 +#define CONFIG_AU1000 1 #else #ifdef CONFIG_DBAU1100 -#define CONFIG_AU1100 1 +#define CONFIG_AU1100 1 #else #ifdef CONFIG_DBAU1500 -#define CONFIG_AU1500 1 -#else +#define CONFIG_AU1500 1 +#else #error "No valid board set" #endif #endif #endif -#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ +#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ @@ -158,7 +158,7 @@ #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR -/* Offset for data I/O */ +/* Offset for data I/O */ #define CFG_ATA_DATA_OFFSET 8 /* Offset for normal register accesses */ |