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authorWolfgang Denk <wd@denx.de>2008-04-08 00:05:42 +0200
committerWolfgang Denk <wd@denx.de>2008-04-08 00:05:42 +0200
commit62479b181460f5bf99517b68059d5ba87908edd3 (patch)
treea68933d5d6b6ab8d06c107c421d6abb5d1669e74 /include/configs/davinci_sonata.h
parent5c395393cc9b85b14c5481dbcab6b67b54f31622 (diff)
parent066bebd6353e33af3adefc3404560871699e9961 (diff)
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Merge branch 'master' of git://www.denx.de/git/u-boot-arm
Diffstat (limited to 'include/configs/davinci_sonata.h')
-rw-r--r--include/configs/davinci_sonata.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index de8c4fa..b2c0d7d 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -60,6 +60,24 @@
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000
+#define CFG_DAVINCI_PINMUX_0 0x00000c1f
+#define CFG_DAVINCI_WAITCFG 0x00000000
+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
+#define CFG_DAVINCI_ACFG3 0x3ffffffd
+#define CFG_DAVINCI_ACFG4 0x3ffffffd
+#define CFG_DAVINCI_ACFG5 0x3ffffffd
+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
+#define CFG_DAVINCI_SDREF 0x000005c3
+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
+#define CFG_DAVINCI_SDTIM0 0x28923211
+#define CFG_DAVINCI_SDTIM1 0x0016c722
+#define CFG_DAVINCI_MMARG_BRF0 0x00444400
+/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
+#define CFG_DAVINCI_PLL1_PLLM 0x15
+#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
+#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
+#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */