Merge 'next' branch

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 52 insertions, 52 deletions

diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
index 19c2836..fa70a09 100644
--- a/include/configs/cmi_mpc5xx.h
+++ b/include/configs/cmi_mpc5xx.h
@@ -93,25 +93,25 @@
  * Miscellaneous configurable options
  */
 
-#define	CFG_LONGHELP				/* undef to save memory		*/
-#define	CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS		16	       /* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	       /* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x000fa000	/* 1 MB in SRAM			*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x000fa000	/* 1 MB in SRAM			*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address		*/
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
 
-#define	CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
 
 
 /*
@@ -121,39 +121,39 @@
 /*
  * Internal Memory Mapped (This is not the IMMR content)
  */
-#define CFG_IMMR		0x01000000		/* Physical start adress of internal memory map */
+#define CONFIG_SYS_IMMR		0x01000000		/* Physical start adress of internal memory map */
 
 /*
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
-#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
-#define	CFG_GBL_DATA_SIZE	64			/* Size in bytes reserved for initial global data */
-#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
-#define	CFG_INIT_SP_ADDR	0x013fa000		/* Physical start adress of inital stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
+#define	CONFIG_SYS_INIT_RAM_END	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64			/* Size in bytes reserved for initial global data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define	CONFIG_SYS_INIT_SP_ADDR	0x013fa000		/* Physical start adress of inital stack */
 
 /*
  * Start addresses for the final memory configuration
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
-#define CFG_FLASH_BASE		0x02000000	/* External flash */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
+#define CONFIG_SYS_FLASH_BASE		0x02000000	/* External flash */
 #define PLD_BASE		0x03000000	/* PLD  */
 #define ANYBUS_BASE		0x03010000	/* Anybus Module */
 
-#define CFG_RESET_ADRESS	0x01000000	/* Adress which causes reset */
-#define	CFG_MONITOR_BASE	CFG_FLASH_BASE	/* TEXT_BASE is defined in the board config.mk file.	*/
+#define CONFIG_SYS_RESET_ADRESS	0x01000000	/* Adress which causes reset */
+#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE	/* TEXT_BASE is defined in the board config.mk file.	*/
 						/* This adress is given to the linker with -Ttext to	*/
 						/* locate the text section at this adress.		*/
-#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor				*/
-#define	CFG_MALLOC_LEN		(64 << 10)	/* Reserve 128 kB for malloc()				*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor				*/
+#define	CONFIG_SYS_MALLOC_LEN		(64 << 10)	/* Reserve 128 kB for malloc()				*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
 
 
 /*-----------------------------------------------------------------------
@@ -162,18 +162,18 @@
  *
  */
 
-#define CFG_MAX_FLASH_BANKS	1		/* Max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	64		/* Max number of sectors on one chip	*/
-#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/
-#define CFG_FLASH_PROTECTION    1		/* Physically section protection on	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* Max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_PROTECTION    1		/* Physically section protection on	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_OFFSET		0x00020000	/* Environment starts at this adress	*/
 #define	CONFIG_ENV_SIZE		0x00010000	/* Set whole sector as env		*/
-#define	CFG_USE_PPCENV				/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV				/* Environment embedded in sect .ppcenv */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -183,10 +183,10 @@
  * SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWP)
 #endif	/* CONFIG_WATCHDOG */
 
@@ -195,14 +195,14 @@
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register
@@ -211,7 +211,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF00
-#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 			 SCCR_COM00   | SCCR_DFNL000 | SCCR_DFNH000)
 
 /*-----------------------------------------------------------------------
@@ -219,7 +219,7 @@
  *-----------------------------------------------------------------------
  * Data show cycle
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00)		/* Disable data show cycle	*/
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00)		/* Disable data show cycle	*/
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register
@@ -227,8 +227,8 @@
  * Set all bits to 40 Mhz
  *
  */
-#define CFG_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
-#define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
+#define CONFIG_SYS_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
+#define CONFIG_SYS_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
 
 
 /*-----------------------------------------------------------------------
@@ -236,36 +236,36 @@
  *-----------------------------------------------------------------------
  *
  */
-#define CFG_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
+#define CONFIG_SYS_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
 
 /*-----------------------------------------------------------------------
  * ICTRL - I-Bus Support Control Register
  */
-#define CFG_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
+#define CONFIG_SYS_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
 
 /*-----------------------------------------------------------------------
  * USIU - Memory Controller Register
  *-----------------------------------------------------------------------
  */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
-#define CFG_OR0_PRELIM		(OR_ADDR_MK_FF | OR_SCY_3)
-#define CFG_BR1_PRELIM		(ANYBUS_BASE)
-#define CFG_OR1_PRELIM		(OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
-#define CFG_BR2_PRELIM		(CFG_SDRAM_BASE | BR_V | BR_PS_32)
-#define CFG_OR2_PRELIM		(OR_ADDR_MK_FF)
-#define CFG_BR3_PRELIM		(PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
-#define CFG_OR3_PRELIM		(OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
+#define CONFIG_SYS_OR0_PRELIM		(OR_ADDR_MK_FF | OR_SCY_3)
+#define CONFIG_SYS_BR1_PRELIM		(ANYBUS_BASE)
+#define CONFIG_SYS_OR1_PRELIM		(OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32)
+#define CONFIG_SYS_OR2_PRELIM		(OR_ADDR_MK_FF)
+#define CONFIG_SYS_BR3_PRELIM		(PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
+#define CONFIG_SYS_OR3_PRELIM		(OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
 				 OR_ACS_10 | OR_ETHR | OR_CSNT)
 
-#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* We don't realign the flash	*/
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* We don't realign the flash	*/
 
 /*-----------------------------------------------------------------------
  * DER - Timer Decrementer
  *-----------------------------------------------------------------------
  * Initialise to zero
  */
-#define CFG_DER			0x00000000
+#define CONFIG_SYS_DER			0x00000000
 
 
 /*