Merge 'next' branch

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 114 insertions, 114 deletions

diff --git a/include/configs/barco.h b/include/configs/barco.h
index 9afb10e..e00f84a 100644
--- a/include/configs/barco.h
+++ b/include/configs/barco.h
@@ -102,14 +102,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 
 /*-----------------------------------------------------------------------
@@ -128,58 +128,58 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x02000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x02000000
 
 #define CONFIG_LOGBUFFER
 #ifdef	CONFIG_LOGBUFFER
-#define CFG_STDOUT_ADDR		0x1FFC000
+#define CONFIG_SYS_STDOUT_ADDR		0x1FFC000
 #else
-#define CFG_STDOUT_ADDR		0x2B9000
+#define CONFIG_SYS_STDOUT_ADDR		0x2B9000
 #endif
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #if defined (USE_DINK32)
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	0x00090000
-#define CFG_RAMBOOT		1
-#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_INIT_RAM_END	0x10000
-#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_END	0x10000
+#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 #else
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-#define CFG_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 #endif
 
-#define CFG_FLASH_BASE		0xFFF00000
-#define CFG_FLASH_SIZE		(8 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
+#define CONFIG_SYS_FLASH_SIZE		(8 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x000047A4	/* Offset of Environment Sector */
 #define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
 /* #define ENV_CRC		0x8BF6F24B	XXX - FIXME: gets defined automatically */
 
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
 
-#define CFG_EUMB_ADDR		0xFDF00000
+#define CONFIG_SYS_EUMB_ADDR		0xFDF00000
 
-#define CFG_FLASH_RANGE_BASE	0xFFC00000	/* flash memory address range	*/
-#define CFG_FLASH_RANGE_SIZE	0x00400000
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFFC00000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x00400000
 #define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
 #define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
 
@@ -192,8 +192,8 @@
  */
 #define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
 #undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 #ifdef CONFIG_SOFT_I2C
 #error "Soft I2C is not configured properly.  Please review!"
@@ -208,14 +208,14 @@
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 #endif /* CONFIG_SOFT_I2C */
 
-#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
-#define CFG_DBUS_SIZE2		1
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+#define CONFIG_SYS_DBUS_SIZE2		1
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
@@ -233,24 +233,24 @@
 
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
 
-#define CFG_ROMNAL		0x0F	/*rom/flash next access time		*/
-#define CFG_ROMFAL		0x1E	/*rom/flash access time			*/
+#define CONFIG_SYS_ROMNAL		0x0F	/*rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		0x1E	/*rom/flash access time			*/
 
-#define CFG_REFINT	0x8F	/* no of clock cycles between CBR refresh cycles */
+#define CONFIG_SYS_REFINT	0x8F	/* no of clock cycles between CBR refresh cycles */
 
 /* the following are for SDRAM only*/
-#define CFG_BSTOPRE	0x25C	/* Burst To Precharge, sets open page interval */
-#define CFG_REFREC		8	/* Refresh to activate interval		*/
-#define CFG_RDLAT		4	/* data latency from read command	*/
-#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		2	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_BSTOPRE	0x25C	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		2	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
 
-#define CFG_REGISTERD_TYPE_BUFFER   1
-#define CFG_EXTROM 0
-#define CFG_REGDIMM 0
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM 0
+#define CONFIG_SYS_REGDIMM 0
 
 
 /* memory bank settings*/
@@ -260,95 +260,95 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		0x01FFFFFF
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x02000000
-#define CFG_BANK1_END		0x02ffffff
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x03f00000
-#define CFG_BANK2_END		0x03ffffff
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x04000000
-#define CFG_BANK3_END		0x04ffffff
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x05000000
-#define CFG_BANK4_END		0x05FFFFFF
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x06000000
-#define CFG_BANK5_END		0x06FFFFFF
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x07000000
-#define CFG_BANK6_END		0x07FFFFFF
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x08000000
-#define CFG_BANK7_END		0x08FFFFFF
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		0x01FFFFFF
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x02000000
+#define CONFIG_SYS_BANK1_END		0x02ffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x03f00000
+#define CONFIG_SYS_BANK2_END		0x03ffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x04000000
+#define CONFIG_SYS_BANK3_END		0x04ffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x05000000
+#define CONFIG_SYS_BANK4_END		0x05FFFFFF
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x06000000
+#define CONFIG_SYS_BANK5_END		0x06FFFFFF
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x07000000
+#define CONFIG_SYS_BANK6_END		0x07FFFFFF
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x08000000
+#define CONFIG_SYS_BANK7_END		0x08FFFFFF
+#define CONFIG_SYS_BANK7_ENABLE	0
 /*
  * Memory bank enable bitmask, specifying which of the banks defined above
  are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 1GB (no backing mem) */
 #if defined(USE_DINK32)
-#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
-#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
 #else
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 #endif
 
 /* PCI memory */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Flash, config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_CHECKSUM
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif