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author | Stefan Roese <sr@denx.de> | 2007-08-14 16:36:29 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2007-08-14 16:36:29 +0200 |
commit | 3b3bff4cbf2cb14f9a3e7d03f26ebab900efe4ae (patch) | |
tree | fb66bf8861d9f78765160d734a438856f5317cdb /include/configs/barco.h | |
parent | 4ce846ec59f36b85d6644a769690ad3feb667575 (diff) | |
parent | 4ef35e53c693556c54b0c22d6f873de87bade253 (diff) | |
download | u-boot-imx-3b3bff4cbf2cb14f9a3e7d03f26ebab900efe4ae.zip u-boot-imx-3b3bff4cbf2cb14f9a3e7d03f26ebab900efe4ae.tar.gz u-boot-imx-3b3bff4cbf2cb14f9a3e7d03f26ebab900efe4ae.tar.bz2 |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/configs/barco.h')
-rw-r--r-- | include/configs/barco.h | 37 |
1 files changed, 22 insertions, 15 deletions
diff --git a/include/configs/barco.h b/include/configs/barco.h index 624fa1d..0bb446f 100644 --- a/include/configs/barco.h +++ b/include/configs/barco.h @@ -70,22 +70,30 @@ #define CONFIG_BOOTARGS "mem=32M" -/* Add support for a few extra bootp options like: - * - File size - * - DNS + +/* + * BOOTP options */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PCI -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_PCI ) +#undef CONFIG_CMD_NET -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> #define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ #define CONFIG_BOOTDELAY 1 @@ -110,7 +118,6 @@ */ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP -#undef CFG_CMD_NET #define PCI_ENET0_IOADDR 0x80000000 #define PCI_ENET0_MEMADDR 0x80000000 @@ -340,7 +347,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif |