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| author | Stefan Roese <sr@denx.de> | 2007-08-15 14:51:27 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-15 14:51:27 +0200 |
| commit | d61ea14885631e58a25feaa81ee82eb464c62d6a (patch) | |
| tree | 27927975039d0a15e6c6d4dfe8f765a76a12820a /include/configs/at91rm9200dk.h | |
| parent | 3ba4c2d68f6541db4677b4aea12071f56e6ff6e6 (diff) | |
| parent | 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7 (diff) | |
| download | u-boot-imx-d61ea14885631e58a25feaa81ee82eb464c62d6a.zip u-boot-imx-d61ea14885631e58a25feaa81ee82eb464c62d6a.tar.gz u-boot-imx-d61ea14885631e58a25feaa81ee82eb464c62d6a.tar.bz2 | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/configs/at91rm9200dk.h')
| -rw-r--r-- | include/configs/at91rm9200dk.h | 42 |
1 files changed, 30 insertions, 12 deletions
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 8fad55d..a65c5f3 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -97,18 +97,31 @@ #define CONFIG_BOOTDELAY 3 /* #define CONFIG_ENV_OVERWRITE 1 */ -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | CFG_CMD_MII |\ - CFG_CMD_DHCP ) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ - CFG_CMD_LOADS )) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_LOADS + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 @@ -150,6 +163,11 @@ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + #define CONFIG_HAS_DATAFLASH 1 #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) #define CFG_MAX_DATAFLASH_BANKS 2 |