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authorroy zang <tie-fei.zang@freescale.com>2007-01-22 13:15:35 +0800
committerZang Tiefei <roy@bus.ap.freescale.net>2007-01-22 13:15:35 +0800
commitee460917afb74767aedc3da095d4fec4a50ba6f8 (patch)
treefdead38c4681fc9adbedd6836792660f933614d3 /include/configs/alpr.h
parenta41969e09b9d886091a804c2ba5f1ab84b084dd3 (diff)
parenta4012396645533aef218354eeba754dff0deace8 (diff)
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Merge branch 'master' into hpc2
Conflicts: drivers/cfi_flash.c The patch by Heiko Schocher <hs@pollux.denx.de> on Jan, 19, 2007 fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support mpc7448hpc2 board.
Diffstat (limited to 'include/configs/alpr.h')
-rw-r--r--include/configs/alpr.h19
1 files changed, 18 insertions, 1 deletions
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index bbe6b76..49027da 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -166,8 +166,23 @@
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
+ "ethprime=ppc_4xx_eth3\0" \
+ "ethact=ppc_4xx_eth3\0" \
+ "autoload=no\0" \
+ "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
+ "actkernel=kernel2\0" \
+ "load_fpga=fpga load 0 ffe00000 10dd9a\0" \
+ "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
+ "rootfstype=jffs2 init=/sbin/init\0" \
+ "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
+ ";bootm 200000\0" \
+ "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
+ "addtty;bootm 200000\0" \
+ "kernel1=run ipconfig load_fpga kernel1_mtd\0" \
+ "kernel2=run ipconfig load_fpga kernel2_mtd\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_BOOTCOMMAND "run kernel2"
#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
@@ -291,6 +306,8 @@
/*-----------------------------------------------------------------------
* Definitions for GPIO setup
*-----------------------------------------------------------------------*/
+#define CFG_GPIO_SHUTDOWN (0x80000000 >> 6)
+#define CFG_GPIO_SSD_EMPTY (0x80000000 >> 9)
#define CFG_GPIO_EREADY (0x80000000 >> 26)
#define CFG_GPIO_REV0 (0x80000000 >> 14)
#define CFG_GPIO_REV1 (0x80000000 >> 15)