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authorStefan Roese <sr@denx.de>2007-06-04 08:17:29 +0200
committerStefan Roese <sr@denx.de>2007-06-04 08:17:29 +0200
commitd7d5204ce2e0985ff2dfdf3a6b5b6a526cdb1c1e (patch)
treec71da8013140d7bd5024dcde5f9cd075d4c012e2 /include/configs/aev.h
parent7ebb4479b07ff294eb4d76e420753a0349f7c93b (diff)
parent19bf91f9628f80a55d4f171df71041574882b3d6 (diff)
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Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/configs/aev.h')
-rw-r--r--include/configs/aev.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 8d9f0a1..6c2a360 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -166,17 +166,17 @@
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
-#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@@ -362,7 +362,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */