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| author | John Rigby <jrigby@freescale.com> | 2008-08-28 13:17:07 -0600 |
|---|---|---|
| committer | John Rigby <jrigby@freescale.com> | 2008-08-28 13:36:43 -0600 |
| commit | 8a490422bed685c9491274ec997f62061d88620b (patch) | |
| tree | d5d8b3471cacd352bf419431c619b742f5aa8589 /include/configs/ads5121.h | |
| parent | 33aa4eac66b71c797bbc13b3afe432a2132947d4 (diff) | |
| download | u-boot-imx-8a490422bed685c9491274ec997f62061d88620b.zip u-boot-imx-8a490422bed685c9491274ec997f62061d88620b.tar.gz u-boot-imx-8a490422bed685c9491274ec997f62061d88620b.tar.bz2 | |
ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon
MPC5121 rev 2 silicon has a new register for controlling how long
CS is asserted after deassertion of ALE in multiplexed mode.
The default is to assert CS together with ALE. The alternative
is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.
The default is wrong for the NOR flash and CPLD on the ADS5121.
This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
it does so conditionally based on silicon rev 2.0 or greater.
Signed-off-by: Martha J Marx <mmarx@silicontkx.com>
Signed-off-by: John Rigby <jrigby@freescale.com>
Diffstat (limited to 'include/configs/ads5121.h')
| -rw-r--r-- | include/configs/ads5121.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 5f74afb..f516c46 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -210,6 +210,7 @@ #define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ #define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ +#define CFG_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ /* Use SRAM for initial stack */ #define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */ |