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authorKim Phillips <kim.phillips@freescale.com>2007-07-06 19:39:48 -0500
committerKim Phillips <kim.phillips@freescale.com>2007-07-06 19:39:48 -0500
commit0459e7d3a0a273064b738aa2e06fd7dcd35eec58 (patch)
tree83b8a3044400cb1463e91410cf0f3732dedd7fb4 /include/configs/acadia.h
parent30d5c04c93084fe0b144646b77eb873957872a8d (diff)
parente80955f07de03fef0196353e77534b2300193c1c (diff)
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Merge git://www.denx.de/git/u-boot
Diffstat (limited to 'include/configs/acadia.h')
-rw-r--r--include/configs/acadia.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 0f447b0..517d130 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -75,7 +75,7 @@
#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */
/* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR 0xF8000000
+#define CFG_OCM_DATA_ADDR 0xf8000000
#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
@@ -159,7 +159,7 @@
*/
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/
+#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)