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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-09-15 22:21:58 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-24 12:04:57 -0500 |
| commit | 202d94875c98b7b573f136c4f353609758ed9733 (patch) | |
| tree | e0af514570c712830620de7fb014415504da698c /include/configs/XPEDITE5200.h | |
| parent | 30d7aae7e82dacf9ae2983fbbf3567515266968b (diff) | |
| download | u-boot-imx-202d94875c98b7b573f136c4f353609758ed9733.zip u-boot-imx-202d94875c98b7b573f136c4f353609758ed9733.tar.gz u-boot-imx-202d94875c98b7b573f136c4f353609758ed9733.tar.bz2 | |
ppc/85xx: Fix LCRR_CLKDIV defines
For some reason the CLKDIV field varies between SoC in how it interprets
the bit values.
All 83xx and early (e500v1) PQ3 devices support:
clk/2: CLKDIV = 2
clk/4: CLKDIV = 4
clk/8: CLKDIV = 8
Newer PQ3 (e500v2) and MPC86xx support:
clk/4: CLKDIV = 2
clk/8: CLKDIV = 4
clk/16: CLKDIV = 8
Ensure that the MPC86xx and MPC85xx still get the same behavior and make
the defines reflect their logical view (not the value of the field).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'include/configs/XPEDITE5200.h')
| -rw-r--r-- | include/configs/XPEDITE5200.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index deda208..d79231b 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -103,7 +103,7 @@ * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) /* * NAND flash configuration |