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| author | wdenk <wdenk> | 2004-04-24 23:23:30 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-04-24 23:23:30 +0000 |
| commit | e9132ea94c0182400895423c21bb04fa81f0b3f4 (patch) | |
| tree | f6b5dcb9afdc85d0ef74a4fe3cda6df0dd9c267c /include/configs/TQM862M.h | |
| parent | 5cf91d6bdc3e60bd43f9ba1bbb97a43ee49b2b2d (diff) | |
| download | u-boot-imx-e9132ea94c0182400895423c21bb04fa81f0b3f4.zip u-boot-imx-e9132ea94c0182400895423c21bb04fa81f0b3f4.tar.gz u-boot-imx-e9132ea94c0182400895423c21bb04fa81f0b3f4.tar.bz2 | |
Clean up the TQM8xx_YYMHz configurations; allow to use the same
binary image for all clock frequencies. Implement run-time
optimization of flash access timing based on the actual bus
frequency.
Diffstat (limited to 'include/configs/TQM862M.h')
| -rw-r--r-- | include/configs/TQM862M.h | 46 |
1 files changed, 4 insertions, 42 deletions
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 914e28a..7ab8559 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -253,16 +253,8 @@ *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit - * - * If this is a 80 MHz or 100 MHz CPU, - * set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100) */ -#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) -#define CFG_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 66 MHz we use a 1:1 clock */ #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CONFIG_80MHz | CONFIG_100MHz */ /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -271,17 +263,9 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */ -#define CFG_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 66 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ SCCR_DFALCD00) -#endif /* CONFIG_80MHz | CONFIG_100MHz */ /*----------------------------------------------------------------------- * PCMCIA stuff @@ -350,24 +334,8 @@ /* * FLASH timing: */ -#if defined(CONFIG_100MHz) -/* 100 MHz CPU - 50 MHz bus: - * ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 | OR_SCY_7_CLK | OR_BI) -#elif defined(CONFIG_80MHz) -/* 80 MHz CPU - 40 MHz bus: - * ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -#elif defined(CONFIG_66MHz) -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_3_CLK | OR_EHTR | OR_BI) -#else /* 50 MHz */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif /*CONFIG_??MHz */ #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -429,15 +397,9 @@ * 80 Mhz => 80.000.000 / Divider = 156 * 100 Mhz => 100.000.000 / Divider = 195 */ -#if defined(CONFIG_100MHz) -#define CFG_MAMR_PTA 195 -#elif defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ + +#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) +#define CFG_MAMR_PTA 98 /* * For 16 MBit, refresh rates could be 31.3 us |