diff options
| author | wdenk <wdenk> | 2003-06-15 22:40:42 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-06-15 22:40:42 +0000 |
| commit | 71f9511803de65a3b98d2f592d418da1d1539f13 (patch) | |
| tree | 4be38a22fc4f588a80aa8cc350ecd5617a211389 /include/configs/TQM862L.h | |
| parent | 487778b781257831aa9b9140dd3c7ad4176e8314 (diff) | |
| download | u-boot-imx-71f9511803de65a3b98d2f592d418da1d1539f13.zip u-boot-imx-71f9511803de65a3b98d2f592d418da1d1539f13.tar.gz u-boot-imx-71f9511803de65a3b98d2f592d418da1d1539f13.tar.bz2 | |
* Fix CONFIG_NET_MULTI support in include/net.h
* Patches by Kyle Harris, 13 Mar 2003:
- Add FAT partition support
- Add command support for FAT
- Add command support for MMC
----
- Add Intel PXA support for video
- Add Intel PXA support for MMC
----
- Enable MMC and FAT for lubbock board
- Other misc changes for lubbock board
Diffstat (limited to 'include/configs/TQM862L.h')
| -rw-r--r-- | include/configs/TQM862L.h | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 1d0aea1..76e66ca 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -179,6 +179,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ @@ -335,7 +336,7 @@ */ #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ /* used to re-map FLASH both when starting from SRAM or FLASH: * restrict access enough to keep SRAM working (if any) @@ -349,10 +350,8 @@ */ #if defined(CONFIG_100MHz) /* 100 MHz CPU - 50 MHz bus: - * 0x...926: 9 = OR_CSNT_SAM + OR_BI; 2 = OR_SCY_2_CLK; 6 = OR_TRLX + OR_EHTR - * ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) + * ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 | OR_SCY_7_CLK | OR_BI) #elif defined(CONFIG_80MHz) /* 80 MHz CPU - 40 MHz bus: * ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ |