diff options
| author | Wolfgang Grandegger <wg@grandegger.com> | 2009-02-11 18:38:24 +0100 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2009-03-23 15:53:41 -0500 |
| commit | 16f2f5a351004129e79e79816697a367fd9e5446 (patch) | |
| tree | 3f65194eb59fc8f49ecdaaecbbdbb929abcd488f /include/configs/TQM85xx.h | |
| parent | 33846df28fa1f4cf96a96c18142d48d813caa892 (diff) | |
| download | u-boot-imx-16f2f5a351004129e79e79816697a367fd9e5446.zip u-boot-imx-16f2f5a351004129e79e79816697a367fd9e5446.tar.gz u-boot-imx-16f2f5a351004129e79e79816697a367fd9e5446.tar.bz2 | |
Add multi-chip NAND support for the TQM8548 modules
This patches configures the NAND UPM-FSL driver with multi-chip
support for the Micron MT29F8G08FAB NAND flash memory on the
TQM8548 modules.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'include/configs/TQM85xx.h')
| -rw-r--r-- | include/configs/TQM85xx.h | 32 |
1 files changed, 7 insertions, 25 deletions
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 72db26c..2ef24cd 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -371,35 +371,17 @@ #define CONFIG_SYS_NAND_CS_DIST 0x200 #define CONFIG_SYS_NAND_SIZE 0x8000 -#define CONFIG_SYS_NAND0_BASE (CONFIG_SYS_CCSRBAR + 0x03010000) -#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) - -#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ - -#if (CONFIG_SYS_MAX_NAND_DEVICE == 1) -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } -#elif (CONFIG_SYS_MAX_NAND_DEVICE == 2) -#define CONFIG_SYS_NAND_QUIET_TEST 1 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ - CONFIG_SYS_NAND1_BASE, \ -} -#elif (CONFIG_SYS_MAX_NAND_DEVICE == 4) -#define CONFIG_SYS_NAND_QUIET_TEST 1 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ - CONFIG_SYS_NAND1_BASE, \ - CONFIG_SYS_NAND2_BASE, \ - CONFIG_SYS_NAND3_BASE, \ -} -#endif +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_CCSRBAR + 0x03010000) + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_NAND_MAX_CHIPS 2 /* Number of chips per device */ /* CS3 for NAND Flash */ -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \ - BR_MS_UPMB | BR_V) +#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA) | \ + BR_PS_8 | BR_MS_UPMB | BR_V) #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI) -#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */ +#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */ #endif /* CONFIG_NAND */ |