rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

1 files changed, 149 insertions, 149 deletions

diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 072608c..1915a73 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -97,8 +97,8 @@
 /* enable I2C and select the hardware/software driver */
 #undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * Software (bit-bang) I2C driver configuration
@@ -116,21 +116,21 @@
 #define CONFIG_I2C_X
 
 /* EEPROM */
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_PAGE_WRITE_BITS	4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-#define CFG_I2C_MULTI_EEPROMS		1	/* more than one eeprom */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1	/* more than one eeprom */
 
 /* I2C RTC */
 #define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
-#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
 
 /* I2C SYSMON (LM75) */
 #define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
 #define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
 
 #else
 #undef CONFIG_HARD_I2C
@@ -176,9 +176,9 @@
  * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
  */
-#define CFG_FCC_ETHERNET
+#define CONFIG_SYS_FCC_ETHERNET
 
-#if defined(CFG_FCC_ETHERNET)
+#if defined(CONFIG_SYS_FCC_ETHERNET)
 #undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
 #define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
 #undef	CONFIG_ETHER_NONE		/* define if ether on something else */
@@ -196,7 +196,7 @@
  *  - RX clk is CLK11
  *  - TX clk is CLK12
  */
-# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
+# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 
 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 
@@ -206,10 +206,10 @@
  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  * - Enable Full Duplex in FSMR
  */
-# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
 
 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 
@@ -221,35 +221,35 @@
 #define MDIO_PORT	2		/* Port C */
 
 #if STK82xx_150
-#define CFG_MDIO_PIN	0x00008000	/* PC16 */
-#define CFG_MDC_PIN	0x00004000	/* PC17 */
+#define CONFIG_SYS_MDIO_PIN	0x00008000	/* PC16 */
+#define CONFIG_SYS_MDC_PIN	0x00004000	/* PC17 */
 #endif
 
 #if STK82xx_100
-#define CFG_MDIO_PIN	0x00000002	/* PC30 */
-#define CFG_MDC_PIN	0x00000001	/* PC31 */
+#define CONFIG_SYS_MDIO_PIN	0x00000002	/* PC30 */
+#define CONFIG_SYS_MDC_PIN	0x00000001	/* PC31 */
 #endif
 
 #if 1
-#define MDIO_ACTIVE	(iop->pdir |=  CFG_MDIO_PIN)
-#define MDIO_TRISTATE	(iop->pdir &= ~CFG_MDIO_PIN)
-#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)
+#define MDIO_ACTIVE	(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE	(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 
-#define MDIO(bit)	if(bit) iop->pdat |=  CFG_MDIO_PIN; \
-			else	iop->pdat &= ~CFG_MDIO_PIN
+#define MDIO(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 
-#define MDC(bit)	if(bit) iop->pdat |=  CFG_MDC_PIN; \
-			else	iop->pdat &= ~CFG_MDC_PIN
+#define MDC(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
 #else
-#define MDIO_ACTIVE	({unsigned long tmp; tmp = iop->pdir; tmp |=  CFG_MDIO_PIN; iop->pdir = tmp;})
-#define MDIO_TRISTATE	({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;})
-#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)
+#define MDIO_ACTIVE	({unsigned long tmp; tmp = iop->pdir; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
+#define MDIO_TRISTATE	({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
+#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 
-#define MDIO(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CFG_MDIO_PIN; iop->pdat = tmp;}\
-			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;}
+#define MDIO(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
+			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
 
-#define MDC(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CFG_MDC_PIN; iop->pdat = tmp;}\
-			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;}
+#define MDC(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
+			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
 #endif
 
 #define MIIDELAY	udelay(1)
@@ -259,7 +259,7 @@
 #define CONFIG_8260_CLKIN	66666666	/* in Hz */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
@@ -300,56 +300,56 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #if 0
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR	0x300000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR	0x300000	/* default load address	*/
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define	CFG_RESET_ADDRESS 0x40000104	/* "bad" address		*/
+#define	CONFIG_SYS_RESET_ADDRESS 0x40000104	/* "bad" address		*/
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * CAN stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_CAN_BASE	0x51000000
-#define	CFG_CAN_SIZE	1
-#define CFG_CAN_BR	((CFG_CAN_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_CAN_BASE	0x51000000
+#define	CONFIG_SYS_CAN_SIZE	1
+#define CONFIG_SYS_CAN_BR	((CONFIG_SYS_CAN_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_UPMC			|\
 			 BRx_V)
 
-#define CFG_CAN_OR	(MEG_TO_AM(CFG_CAN_SIZE)	|\
+#define CONFIG_SYS_CAN_OR	(MEG_TO_AM(CONFIG_SYS_CAN_SIZE)	|\
 			 ORxU_BI)
 
 
@@ -357,31 +357,31 @@
  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
  * The main FLASH is whichever is connected to *CS0.
  */
-#define CFG_FLASH0_BASE 0x40000000
-#define CFG_FLASH0_SIZE 32	/* 32 MB */
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH0_SIZE 32	/* 32 MB */
 
 /* Flash bank size (for preliminary settings)
  */
-#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_CFI				/* flash is CFI compat.	*/
+#define CONFIG_SYS_FLASH_CFI				/* flash is CFI compat.	*/
 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
-#define CFG_UPDATE_FLASH_SIZE
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
 
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
 #define CONFIG_ENV_SIZE		0x20000
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
@@ -389,14 +389,14 @@
 
 /* Where is the Hardwareinformation Block (from Monitor Sources) */
 #define MON_RES_LENGTH		(0x0003FC00)
-#define HWIB_INFO_START_ADDR    (CFG_FLASH_BASE + MON_RES_LENGTH)
+#define HWIB_INFO_START_ADDR    (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
 #define HWIB_INFO_LEN           512
-#define CIB_INFO_START_ADDR     (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
+#define CIB_INFO_START_ADDR     (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
 #define CIB_INFO_LEN            512
 
-#define CFG_HWINFO_OFFSET	0x3fc00	/* offset of HW Info block */
-#define CFG_HWINFO_SIZE		0x00000060	/* size   of HW Info block */
-#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET	0x3fc00	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000060	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
 
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
@@ -404,32 +404,32 @@
  */
 #if defined(CONFIG_CMD_NAND)
 
-#define CFG_NAND_CS_DIST		0x80
-#define CFG_NAND_UPM_WRITE_CMD_OFS	0x20
-#define CFG_NAND_UPM_WRITE_ADDR_OFS	0x40
+#define CONFIG_SYS_NAND_CS_DIST		0x80
+#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS	0x20
+#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS	0x40
 
-#define CFG_NAND_BR	((CFG_NAND0_BASE & BRx_BA_MSK)	|\
+#define CONFIG_SYS_NAND_BR	((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK)	|\
 			 BRx_PS_8			|\
 			 BRx_MS_UPMB			|\
 			 BRx_V)
 
-#define CFG_NAND_OR	(MEG_TO_AM(CFG_NAND_SIZE)	|\
+#define CONFIG_SYS_NAND_OR	(MEG_TO_AM(CONFIG_SYS_NAND_SIZE)	|\
 			 ORxU_BI			|\
 			 ORxU_EHTR_8IDLE)
 
-#define CFG_NAND_SIZE	1
-#define CFG_NAND0_BASE 0x50000000
-#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
-#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
-#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
+#define CONFIG_SYS_NAND_SIZE	1
+#define CONFIG_SYS_NAND0_BASE 0x50000000
+#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
+#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
+#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
 
-#define CFG_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
+#define CONFIG_SYS_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
 #define NAND_MAX_CHIPS 1
 
-#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
-			     CFG_NAND1_BASE, \
-			     CFG_NAND2_BASE, \
-			     CFG_NAND3_BASE, \
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
+			     CONFIG_SYS_NAND1_BASE, \
+			     CONFIG_SYS_NAND2_BASE, \
+			     CONFIG_SYS_NAND3_BASE, \
 			   }
 
 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
@@ -447,58 +447,58 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 #define CONFIG_PCI_PNP
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
 #define CONFIG_PCI_SCAN_SHOW
 #endif
 
 /*-----------------------------------------------------------------------
  * Hard Reset Configuration Words
  *
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  */
 #if 0
 #define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 
-#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
 #else
-#define CFG_HRCW_MASTER	(HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
 #endif
 
 /* no slaves so just fill with zeros */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFFF00000
+#define CONFIG_SYS_IMMR		0xFFF00000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
-#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		CFG_FLASH0_BASE
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
 
 /*
  * Internal Definitions
@@ -511,9 +511,9 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 #if defined(CONFIG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -526,35 +526,35 @@
  *
  * HID1 has only read-only information - nothing to set.
  */
-#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 				HID0_IFEM|HID0_ABE)
-#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CFG_HID2        0
+#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
 
 /*-----------------------------------------------------------------------
  * RMR - Reset Mode Register                                     5-5
  *-----------------------------------------------------------------------
  * turn on Checkstop Reset Enable
  */
-#define CFG_RMR         RMR_CSRE
+#define CONFIG_SYS_RMR         RMR_CSRE
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration                                       4-25
  *-----------------------------------------------------------------------
  */
-#define CFG_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)	/* 60x mode  */
+#define CONFIG_SYS_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)	/* 60x mode  */
 #define BCR_APD01	0x10000000
-#define CFG_BCR_SINGLE		(BCR_APD01|BCR_ETM)	/* 8260 mode */
+#define CONFIG_SYS_BCR_SINGLE		(BCR_APD01|BCR_ETM)	/* 8260 mode */
 
 /*-----------------------------------------------------------------------
  * SIUMCR - SIU Module Configuration                             4-31
  *-----------------------------------------------------------------------
  */
 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
-#define CFG_SIUMCR_LOW		(SIUMCR_DPPC00)
-#define CFG_SIUMCR_HIGH		(SIUMCR_DPPC00 | SIUMCR_ABE)
+#define CONFIG_SYS_SIUMCR_LOW		(SIUMCR_DPPC00)
+#define CONFIG_SYS_SIUMCR_HIGH		(SIUMCR_DPPC00 | SIUMCR_ABE)
 #else
-#define CFG_SIUMCR		(SIUMCR_DPPC00)
+#define CONFIG_SYS_SIUMCR		(SIUMCR_DPPC00)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -564,10 +564,10 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
-#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 			 SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
@@ -577,7 +577,7 @@
  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  * and enable Time Counter
  */
-#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control                 4-42
@@ -585,20 +585,20 @@
  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  * Periodic timer
  */
-#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  * Ensure DFBRG is Divide by 16
  */
-#define CFG_SCCR        SCCR_DFBRG01
+#define CONFIG_SYS_SCCR        SCCR_DFBRG01
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
  *-----------------------------------------------------------------------
  */
-#define CFG_RCCR        0
+#define CONFIG_SYS_RCCR        0
 
 /*
  * Init Memory Controller:
@@ -614,16 +614,16 @@
 
 /* Initialize SDRAM
 	 */
-#undef CFG_INIT_LOCAL_SDRAM		/* No SDRAM on Local Bus */
+#undef CONFIG_SYS_INIT_LOCAL_SDRAM		/* No SDRAM on Local Bus */
 
 #define SDRAM_MAX_SIZE	0x20000000	/* max. 512 MB		*/
 
 /* Minimum mask to separate preliminary
  * address ranges for CS[0:2]
  */
-#define CFG_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
 
-#define CFG_MPTPR       0x4000
+#define CONFIG_SYS_MPTPR       0x4000
 
 /*-----------------------------------------------------------------------------
  * Address for Mode Register Set (MRS) command
@@ -640,16 +640,16 @@
  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
  *-----------------------------------------------------------------------------
  */
-#define CFG_MRS_OFFS	0x00000110
+#define CONFIG_SYS_MRS_OFFS	0x00000110
 
 /* Bank 0 - FLASH
  */
-#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_32                      |\
 			 BRx_MS_GPCM_P                  |\
 			 BRx_V)
 
-#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 			 ORxG_CSNT                      |\
 			 ORxG_ACS_DIV4                  |\
 			 ORxG_SCY_8_CLK                 |\
@@ -661,25 +661,25 @@
 
 /* Bank 1 - 60x bus SDRAM
  */
-#define CFG_PSRT        0x20	/* Low Value */
-/* #define CFG_PSRT        0x10	 Fast Value */
-#define CFG_LSRT        0x20	/* Local Bus */
-#ifndef CFG_RAMBOOT
-#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+#define CONFIG_SYS_PSRT        0x20	/* Low Value */
+/* #define CONFIG_SYS_PSRT        0x10	 Fast Value */
+#define CONFIG_SYS_LSRT        0x20	/* Local Bus */
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR1_PRELIM	CFG_OR1_8COL
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
 
 /* SDRAM initialization values for 8-column chips
  */
-#define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A7             |\
 			 ORxS_NUMR_12)
 
-#define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A15_IS_A5           |\
 			 PSDMR_BSMA_A12_A14             |\
 			 PSDMR_SDA10_PBI1_A8            |\
@@ -695,12 +695,12 @@
 
 /* SDRAM initialization values for 9-column chips
  */
-#define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A5             |\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A16_IS_A5           |\
 			 PSDMR_BSMA_A12_A14             |\
 			 PSDMR_SDA10_PBI1_A7            |\
@@ -713,12 +713,12 @@
 			 PSDMR_BUFCMD			|\
 			 PSDMR_CL_2)
 
-#define CFG_OR1_10COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CONFIG_SYS_OR1_10COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI1_A4             |\
 			 ORxS_NUMR_13)
 
-#define CFG_PSDMR_10COL  (PSDMR_PBI                      |\
+#define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 			 PSDMR_SDAM_A17_IS_A5           |\
 			 PSDMR_BSMA_A12_A14             |\
 			 PSDMR_SDA10_PBI1_A4            |\
@@ -759,6 +759,6 @@
 #define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
 #define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 #endif	/* __CONFIG_H */