Merge git://git.denx.de/u-boot into x1

Conflicts:

	drivers/usb/usb_ohci.c

1 files changed, 97 insertions, 97 deletions

diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index 3818368..046948e 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -45,7 +45,7 @@
 #define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
 #define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */
 
-#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -57,7 +57,7 @@
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
 #define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
 #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
@@ -139,8 +139,8 @@
  * MUST be low boot - HIGHBOOT is not supported anymore
  */
 #if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
-#   define CFG_LOWBOOT		1
-#   define CFG_LOWBOOT16	1
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
 #else
 #   error "TEXT_BASE must be 0xff000000"
 #endif
@@ -178,7 +178,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
@@ -186,11 +186,11 @@
 /*
  * EEPROM configuration
  */
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
 
-#define CFG_I2C_EEPROM_ADDR_LEN 2
-#define CFG_EEPROM_SIZE 0x2000
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_SIZE 0x2000
 
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_MISC_INIT_R
@@ -201,11 +201,11 @@
 #if defined (CONFIG_SOFT_I2C)
 #  define SDA0			0x40
 #  define SCL0			0x80
-#  define GPIOE0		*((volatile uchar*)(CFG_MBAR+0x0c00))
-#  define DDR0			*((volatile uchar*)(CFG_MBAR+0x0c08))
-#  define DVO0			*((volatile uchar*)(CFG_MBAR+0x0c0c))
-#  define DVI0			*((volatile uchar*)(CFG_MBAR+0x0c20))
-#  define ODE0			*((volatile uchar*)(CFG_MBAR+0x0c04))
+#  define GPIOE0		*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
+#  define DDR0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
+#  define DVO0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
+#  define DVI0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
+#  define ODE0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
 #  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
 #  define I2C_READ		((DVI0&SDA0)?1:0)
 #  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
@@ -213,32 +213,32 @@
 #  define I2C_DELAY		{udelay(5);}
 #  define I2C_ACTIVE	{DDR0|=SDA0;}
 #  define I2C_TRISTATE	{DDR0&=~SDA0;}
-#  define CFG_I2C_SPEED		100000
-#  define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_EEPROM_ADDR 0x57
-#define CFG_I2C_FACT_ADDR	0x57
+#  define CONFIG_SYS_I2C_SPEED		100000
+#  define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_FACT_ADDR	0x57
 #endif
 
 #if defined (CONFIG_HARD_I2C)
-#  define CFG_I2C_MODULE	2		/* Select I2C module #1 or #2 */
-#  define CFG_I2C_SPEED		100000	/* 100 kHz */
-#  define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_EEPROM_ADDR 0x54
-#define CFG_I2C_FACT_ADDR	0x54
+#  define CONFIG_SYS_I2C_MODULE	2		/* Select I2C module #1 or #2 */
+#  define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
+#  define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_FACT_ADDR	0x54
 #endif
 
 /*
  * Flash configuration, expect one 16 Megabyte Bank at most
  */
-#define CFG_FLASH_BASE		0xff000000
-#define CFG_FLASH_SIZE		0x01000000
-#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0)
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0)
 
-#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
 #undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
 
@@ -247,25 +247,25 @@
  */
 #if 0
 /* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
-#define	CFG_DRAM_DDR		0
-#define CFG_DRAM_EMODE		0
-#define CFG_DRAM_MODE		0x008D
-#define CFG_DRAM_CONTROL	0x514F0000
-#define CFG_DRAM_CONFIG1	0xC2233A00
-#define CFG_DRAM_CONFIG2	0x88B70004
-#define	CFG_DRAM_TAP_DEL	0x08
-#define CFG_DRAM_RAM_SIZE	0x19
+#define	CONFIG_SYS_DRAM_DDR		0
+#define CONFIG_SYS_DRAM_EMODE		0
+#define CONFIG_SYS_DRAM_MODE		0x008D
+#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
+#define CONFIG_SYS_DRAM_CONFIG1	0xC2233A00
+#define CONFIG_SYS_DRAM_CONFIG2	0x88B70004
+#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
+#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
 #endif
 #if 1
 /* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
-#define	CFG_DRAM_DDR		0
-#define CFG_DRAM_EMODE		0
-#define CFG_DRAM_MODE		0x00CD
-#define CFG_DRAM_CONTROL	0x514F0000
-#define CFG_DRAM_CONFIG1	0xD2333A00
-#define CFG_DRAM_CONFIG2	0x8AD70004
-#define	CFG_DRAM_TAP_DEL	0x08
-#define CFG_DRAM_RAM_SIZE	0x19
+#define	CONFIG_SYS_DRAM_DDR		0
+#define CONFIG_SYS_DRAM_EMODE		0
+#define CONFIG_SYS_DRAM_MODE		0x00CD
+#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
+#define CONFIG_SYS_DRAM_CONFIG1	0xD2333A00
+#define CONFIG_SYS_DRAM_CONFIG2	0x8AD70004
+#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
+#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
 #endif
 
 /*
@@ -278,35 +278,35 @@
 /*
  * VPD settings
  */
-#define CFG_FACT_OFFSET		0x1800
-#define CFG_FACT_SIZE		0x0800
+#define CONFIG_SYS_FACT_OFFSET		0x1800
+#define CONFIG_SYS_FACT_SIZE		0x0800
 
 /*
  * Memory map
  *
  * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
  */
-#define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
 
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE    TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Ethernet configuration
@@ -321,32 +321,32 @@
  * PCI disabled
  * Ethernet 100 with MD
  */
-#define CFG_GPS_PORT_CONFIG	0x00058044
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044
 
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#  define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x200000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 
@@ -354,12 +354,12 @@
   #define CONFIG_RTC_MK48T59	1	/* use M48T08 on EVAL5200 */
   #define RTC(reg)		(0xf0010000+reg)
   /* setup CS2 for M48T08. Must MAP 64kB */
-  #define CFG_CS2_START	RTC(0)
-  #define CFG_CS2_SIZE	0x10000
+  #define CONFIG_SYS_CS2_START	RTC(0)
+  #define CONFIG_SYS_CS2_SIZE	0x10000
   /* setup CS2 configuration register: */
   /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
   /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
-  #define CFG_CS2_CFG	0x00047800
+  #define CONFIG_SYS_CS2_CFG	0x00047800
 #else
   #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
 #endif
@@ -367,19 +367,19 @@
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
-#define CFG_BOOTCS_START	CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047801
-#define CFG_CS0_START		CFG_FLASH_BASE
-#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
 
-#define CFG_CS_BURST		0x00000000
-#define CFG_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
 
-#define CFG_RESET_ADDRESS	0x7f000000
+#define CONFIG_SYS_RESET_ADDRESS	0x7f000000
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff Supports IDE harddisk
@@ -394,23 +394,23 @@
 #define CONFIG_IDE_RESET	1
 #define CONFIG_IDE_PREINIT
 
-#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
 
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
 
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
 
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	(0x005c)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005c)
 
 /* Interval between registers                                                */
-#define CFG_ATA_STRIDE          4
+#define CONFIG_SYS_ATA_STRIDE          4
 
 #endif /* __CONFIG_H */