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| author | TsiChung Liew <Tsi-Chung.Liew@freescale.com> | 2008-10-21 10:03:07 +0000 |
|---|---|---|
| committer | John Rigby <jrigby@freescale.com> | 2008-11-03 09:45:58 -0700 |
| commit | 012522fef3b382469125beb46a315ab4dee02fb0 (patch) | |
| tree | 9bc6b0cc47ec08dd3efb07a75eaa50fd04ec5f32 /include/configs/TASREG.h | |
| parent | ac2331aee99ad36be0fcfed8c49922e3c61b576d (diff) | |
| download | u-boot-imx-012522fef3b382469125beb46a315ab4dee02fb0.zip u-boot-imx-012522fef3b382469125beb46a315ab4dee02fb0.tar.gz u-boot-imx-012522fef3b382469125beb46a315ab4dee02fb0.tar.bz2 | |
ColdFire: Modules header files cleanup
Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG,
MDHA, SKHA, INTC, and FlexBus structures and
definitions in immap_5xxx.h to more unify modules
header files. Append DSPI support for m547x_8x.
SSI cleanup. Remove USB Host structure from immap_539.h.
Apply changes to use FlexBus structures in mcf52x2's
cpu_init.c and platform configuration files.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Diffstat (limited to 'include/configs/TASREG.h')
| -rw-r--r-- | include/configs/TASREG.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 18ffbfd..25f3a26 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -206,7 +206,7 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffc00000 +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #if 0 /* test-only */ #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ @@ -257,15 +257,15 @@ */ /* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CSAR0 0xffc0 -#define CONFIG_SYS_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */ +#define CONFIG_SYS_CS0_BASE 0xffc00000 +#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ -#define CONFIG_SYS_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ +#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ /* CS1 - FPGA, address 0xe0000000 */ -#define CONFIG_SYS_CSAR1 0xe000 -#define CONFIG_SYS_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */ -#define CONFIG_SYS_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ +#define CONFIG_SYS_CS1_BASE 0xe0000000 +#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ +#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ /*----------------------------------------------------------------------- * Port configuration |