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| author | Tom Rini <trini@ti.com> | 2013-07-24 09:22:28 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-07-24 09:50:24 -0400 |
| commit | c2120fbfbc4d1f6953228f86be8bdbf38bacfdab (patch) | |
| tree | 14cd8ec9a0a61f7113149be38d79808cd5e955f8 /include/configs/TASREG.h | |
| parent | e85427fd66a21b39145a47e67871a8863c0e5591 (diff) | |
| parent | ecbd7e1ec7280d90d151a99691f74b892588cadd (diff) | |
| download | u-boot-imx-c2120fbfbc4d1f6953228f86be8bdbf38bacfdab.zip u-boot-imx-c2120fbfbc4d1f6953228f86be8bdbf38bacfdab.tar.gz u-boot-imx-c2120fbfbc4d1f6953228f86be8bdbf38bacfdab.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-i2c
The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.
Conflicts:
board/sandburst/common/ppc440gx_i2c.c
board/sandburst/common/ppc440gx_i2c.h
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'include/configs/TASREG.h')
| -rw-r--r-- | include/configs/TASREG.h | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 494ed07..bce4176 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -120,19 +120,11 @@ /*----------------------------------------------------------------------- * I2C */ -#define CONFIG_SOFT_I2C -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SOFT_SPEED 100000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#if defined (CONFIG_SOFT_I2C) #if 0 /* push-pull */ #define SDA 0x00800000 #define SCL 0x00000008 @@ -166,7 +158,17 @@ #define I2C_ACTIVE {DIR1|=SDA;} #define I2C_TRISTATE {DIR1&=~SDA;} #endif -#endif + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 +/* + * The Catalyst CAT24WC32 has 32 byte page write mode using + * last 5 bits of the address + */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) |