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| author | Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> | 2014-12-08 14:54:01 -0500 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-12-15 09:16:07 -0800 |
| commit | 3fa66db4599d852c1ee6cb889ecca425c9c3047b (patch) | |
| tree | 6ced11db40aa26667f7c4d7d7f9e11239d579871 /include/configs/T102xRDB.h | |
| parent | 24d827f526d48e21868b5d869bd81a7fa148a0ba (diff) | |
| download | u-boot-imx-3fa66db4599d852c1ee6cb889ecca425c9c3047b.zip u-boot-imx-3fa66db4599d852c1ee6cb889ecca425c9c3047b.tar.gz u-boot-imx-3fa66db4599d852c1ee6cb889ecca425c9c3047b.tar.bz2 | |
mpc85xx: inhibit qman and bman portals by default
Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is required when supporting power management.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/configs/T102xRDB.h')
| -rw-r--r-- | include/configs/T102xRDB.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 6f1fcd6..de9b585 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -685,6 +685,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #endif #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ + CONFIG_SYS_BMAN_CENA_SIZE) +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #ifdef CONFIG_PHYS_64BIT @@ -693,6 +701,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ + CONFIG_SYS_QMAN_CENA_SIZE) +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 #define CONFIG_SYS_DPAA_FMAN |