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| author | wdenk <wdenk> | 2003-07-17 23:16:40 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-07-17 23:16:40 +0000 |
| commit | 2535d60277cc295adf75cd5721dcecd840c69a63 (patch) | |
| tree | a4a7c42580ded1e631658cec4f7a26d8e677a342 /include/configs/SPD823TS.h | |
| parent | 945af8d723a29e9b6289d84250745ed0dc16fc81 (diff) | |
| download | u-boot-imx-2535d60277cc295adf75cd5721dcecd840c69a63.zip u-boot-imx-2535d60277cc295adf75cd5721dcecd840c69a63.tar.gz u-boot-imx-2535d60277cc295adf75cd5721dcecd840c69a63.tar.bz2 | |
* Patch by Martin Krause, 17 Jul 2003:
add delay to get I2C working with "imm" command and s3c24x0_i2c.c
* Patch by Richard Woodruff, 17 July 03:
- Fixed bug in OMAP1510 baud rate divisor settings.
* Patch by Nye Liu, 16 July 2003:
MPC860FADS fixes:
- add MPC86xADS support (uses MPC86xADS.h)
- add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
o PLPRCR changes
o BRG changes (EXTAL/XTAL restricted to 10MHz)
o don't trust gclk() software measurement by default, depend on
CONFIG_8xx_GCLK_FREQ
- add DRAM SIMM not installed detection
- use more "correct" SDRAM initialization sequence
- allow different SDRAM sizes (8xxADS has 8M)
- default DER is 0
- remove unused MAMR defines from FADS860T.h (all done in fads.c)
- rename MAMR/MBMR defines to be more consistent. Should eventually
be merged into MxMR to better reflect the PowerQUICC datasheet.
* Patch by Yuli Barcohen, 16 Jul 2003:
support new Motorola PQ2FADS-ZU evaluation board which replaced
MPC8260ADS and MPC8266ADS
Diffstat (limited to 'include/configs/SPD823TS.h')
| -rw-r--r-- | include/configs/SPD823TS.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index 51f2c25..ae4dcc2 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -381,7 +381,7 @@ */ /* periodic timer for refresh */ -#define CFG_MAMR_PTB 204 +#define CFG_MBMR_PTB 204 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ @@ -396,9 +396,9 @@ */ /* 8 column SDRAM */ -#define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \ - MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 | \ - MAMR_RLFB_1X | MAMR_WLFB_1X | MAMR_TLFB_4X) +#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) /* * Internal Definitions |