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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-08-26 23:52:58 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-08-27 11:43:52 -0500 |
| commit | 8e55313b7ae12352a343f9b9962e662dbd897187 (patch) | |
| tree | 6181c86879fee4598e31b754db70c96b40964210 /include/configs/SBC8540.h | |
| parent | 9658bec2e8f55d56ca1be70090ce5a348be4980f (diff) | |
| download | u-boot-imx-8e55313b7ae12352a343f9b9962e662dbd897187.zip u-boot-imx-8e55313b7ae12352a343f9b9962e662dbd897187.tar.gz u-boot-imx-8e55313b7ae12352a343f9b9962e662dbd897187.tar.bz2 | |
FSL DDR: Convert SBC8560 to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/SBC8540.h')
| -rw-r--r-- | include/configs/SBC8540.h | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 6033d93..93509ee 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -103,18 +103,34 @@ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE #define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ -#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ +/* DDR Setup */ +#define CONFIG_FSL_DDR1 +#undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_SPD #if defined(CONFIG_MPC85xx_REV1) #define CONFIG_DDR_DLL /* possible DLL fix needed */ #endif +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CFG_DDR_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */ + #undef CONFIG_CLOCKS_IN_MHZ #if defined(CONFIG_RAM_AS_FLASH) |