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authorDave Liu <daveliu@freescale.com>2008-12-02 11:48:51 +0800
committerScott Wood <scottwood@freescale.com>2009-01-23 10:32:50 -0600
commitc70564e6b1bd08f3230182392238907f3531a87e (patch)
tree08210e54577641c2567a0bcf3ad981855df43dea /include/configs/PPChameleonEVB.h
parent50657c273278f74378e1ac39b41d612b92fdffa0 (diff)
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NAND: Fix cache and memory inconsistency issue
We load the secondary stage u-boot image from NAND to system memory by nand_load, but we did not flush d-cache to memory, nor invalidate i-cache before we jump to RAM. When the system has cache enabled and the TLB/page attribute of system memory is cacheable, it will cause issues. - 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue. - 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue. This patch fixes the cache issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'include/configs/PPChameleonEVB.h')
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