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authorBartlomiej Sieka <tur@semihalf.com>2006-02-24 09:37:22 +0100
committerBartlomiej Sieka <tur@pollux.(none)>2006-02-24 09:37:22 +0100
commit038ccac511214b062c56f22b9413f784b86bcd87 (patch)
tree9925a8bb04e791550c76e864c5821b12fc478e2e /include/configs/PPChameleonEVB.h
parent84e106c09d324e345f335d2edef246d0b4c9131a (diff)
parent8e9655f863246db60c51140153186acc2afdc855 (diff)
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Merge with /home/wd/git/u-boot/testing-NAND/ to add new NAND handling.
Diffstat (limited to 'include/configs/PPChameleonEVB.h')
-rw-r--r--include/configs/PPChameleonEVB.h90
1 files changed, 86 insertions, 4 deletions
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 7ca827f..c406c8f 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -188,10 +188,14 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
+
+/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
+#define CONFIG_NEW_NAND_CODE
#define CFG_NAND0_BASE 0xFF400000
#define CFG_NAND1_BASE 0xFF000000
-
-#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, CFG_NAND1_BASE }
+#define NAND_BIG_DELAY_US 25
+#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
#define SECTORSIZE 512
#define NAND_NO_RB
@@ -213,6 +217,83 @@
#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
+#ifdef CONFIG_NEW_NAND_CODE
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
+{ \
+ switch((unsigned long)nandptr) \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+ break; \
+ } \
+} while(0)
+
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
+ switch((unsigned long)nandptr) { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+ break; \
+ } \
+} while(0)
+#else
#define NAND_DISABLE_CE(nand) do \
{ \
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
@@ -288,6 +369,7 @@
break; \
} \
} while(0)
+#endif /* !CONFIG_NEW_NAND_CODE */
#ifdef NAND_NO_RB
/* constant delay (see also tR in the datasheet) */
@@ -338,16 +420,16 @@
#define CFG_SDRAM_BASE 0x00000000
/* Reserve 256 kB for Monitor */
+/*
#define CFG_FLASH_BASE 0xFFFC0000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (256 * 1024)
+*/
/* Reserve 320 kB for Monitor */
-/*
#define CFG_FLASH_BASE 0xFFFB0000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (320 * 1024)
-*/
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */