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| author | Stefan Roese <sr@denx.de> | 2010-09-11 09:31:43 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-09-23 09:02:05 +0200 |
| commit | 5e7abce99163a00b8d267cc8045f06b498728288 (patch) | |
| tree | 33da20a6f8524f7a8929cc4f8c003708a5f0a6e8 /include/configs/PPChameleonEVB.h | |
| parent | 098877628888f28f321b8a61a9b0b982a969e415 (diff) | |
| download | u-boot-imx-5e7abce99163a00b8d267cc8045f06b498728288.zip u-boot-imx-5e7abce99163a00b8d267cc8045f06b498728288.tar.gz u-boot-imx-5e7abce99163a00b8d267cc8045f06b498728288.tar.bz2 | |
ppc4xx: Big header cleanup, mostly PPC440 related
This patch starts a bit PPC4xx header cleanup. First patch mostly
touches PPC440 files. A later patch will touch the PPC405 files as well.
This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/PPChameleonEVB.h')
| -rw-r--r-- | include/configs/PPChameleonEVB.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 44f03dc..09f3544 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -577,17 +577,6 @@ #define DIMM_READ_ADDR 0xAB #define DIMM_WRITE_ADDR 0xAA -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - /* Defines for CPC0_PLLMR1 Register fields */ #define PLL_ACTIVE 0x80000000 #define CPC0_PLLMR1_SSCS 0x80000000 |