Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

1 files changed, 97 insertions, 97 deletions

diff --git a/include/configs/PN62.h b/include/configs/PN62.h
index da7d8b8..2c0774f 100644
--- a/include/configs/PN62.h
+++ b/include/configs/PN62.h
@@ -99,14 +99,14 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP		1		/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_PRAM		1024		/* reserve 1 MB protected RAM	*/
 
@@ -139,50 +139,50 @@
 /*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x10000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
 
-#define CFG_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
 
-#undef	CFG_RAMBOOT
-#define CFG_MONITOR_LEN		0x00030000
-#define CFG_MONITOR_BASE	TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
 
-/*#define CFG_GBL_DATA_SIZE    256*/
-#define CFG_GBL_DATA_SIZE	128
+/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define CFG_INIT_RAM_END	0x1000
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_END	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 
 
-#define CFG_NO_FLASH		1		/* There is no FLASH memory	*/
+#define CONFIG_SYS_NO_FLASH		1		/* There is no FLASH memory	*/
 
-#define CFG_ENV_IS_NOWHERE	1		/* Store ENV in memory only	*/
-#define CFG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
+#define CONFIG_ENV_IS_NOWHERE	1		/* Store ENV in memory only	*/
+#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
+#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
 
-#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 
-#define CFG_MEMTEST_START	0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x01f00000	/* 0 ... 32 MB in DRAM		*/
+#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 0 ... 32 MB in DRAM		*/
 
 /*
  * Serial port configuration
  */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
 
-#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		1843200
+#define CONFIG_SYS_NS16550_CLK		1843200
 
-#define CFG_NS16550_COM1	0xff800008
-#define CFG_NS16550_COM2	0xff800000
+#define CONFIG_SYS_NS16550_COM1	0xff800008
+#define CONFIG_SYS_NS16550_COM2	0xff800000
 
 /*
  * Low Level Configuration Settings
@@ -193,30 +193,30 @@
 #define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  3
 
-#define CFG_EUMB_ADDR		0xFCE00000
+#define CONFIG_SYS_EUMB_ADDR		0xFCE00000
 
 /* MCCR1 */
-#define CFG_ROMNAL		3	/* rom/flash next access time		*/
-#define CFG_ROMFAL		7	/* rom/flash access time		*/
+#define CONFIG_SYS_ROMNAL		3	/* rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		7	/* rom/flash access time		*/
 
 /* MCCR2 */
-#define CFG_ASRISE		6	/* ASRISE in clocks			*/
-#define CFG_ASFALL		12	/* ASFALL in clocks			*/
-#define CFG_REFINT		5600	/* REFINT in clocks			*/
+#define CONFIG_SYS_ASRISE		6	/* ASRISE in clocks			*/
+#define CONFIG_SYS_ASFALL		12	/* ASFALL in clocks			*/
+#define CONFIG_SYS_REFINT		5600	/* REFINT in clocks			*/
 
 /* MCCR3 */
-#define CFG_BSTOPRE		0x3cf	/* Burst To Precharge			*/
-#define CFG_REFREC		2	/* Refresh to activate interval		*/
-#define CFG_RDLAT		3	/* data latency from read command	*/
+#define CONFIG_SYS_BSTOPRE		0x3cf	/* Burst To Precharge			*/
+#define CONFIG_SYS_REFREC		2	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		3	/* data latency from read command	*/
 
 /* MCCR4 */
-#define CFG_PRETOACT		1	/* Precharge to activate interval	*/
-#define CFG_ACTTOPRE		3	/* Activate to Precharge interval	*/
-#define CFG_ACTORW		2	/* Activate to R/W			*/
-#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
-#define CFG_SDMODE_WRAP		0	/* SDMODE Wrap type			*/
-#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
-#define CFG_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_PRETOACT		1	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		3	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		2	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE Wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
 
 /* Memory bank settings:
  *
@@ -225,80 +225,80 @@
  * bits will be set to 0x00000 for a start address, or 0xfffff for an
  * end address
  */
-#define CFG_BANK0_START		0x00000000
-#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE	1
-#define CFG_BANK1_START		0x00000000
-#define CFG_BANK1_END		0x00000000
-#define CFG_BANK1_ENABLE	0
-#define CFG_BANK2_START		0x00000000
-#define CFG_BANK2_END		0x00000000
-#define CFG_BANK2_ENABLE	0
-#define CFG_BANK3_START		0x00000000
-#define CFG_BANK3_END		0x00000000
-#define CFG_BANK3_ENABLE	0
-#define CFG_BANK4_START		0x00000000
-#define CFG_BANK4_END		0x00000000
-#define CFG_BANK4_ENABLE	0
-#define CFG_BANK5_START		0x00000000
-#define CFG_BANK5_END		0x00000000
-#define CFG_BANK5_ENABLE	0
-#define CFG_BANK6_START		0x00000000
-#define CFG_BANK6_END		0x00000000
-#define CFG_BANK6_ENABLE	0
-#define CFG_BANK7_START		0x00000000
-#define CFG_BANK7_END		0x00000000
-#define CFG_BANK7_ENABLE	0
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x00000000
+#define CONFIG_SYS_BANK1_END		0x00000000
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x00000000
+#define CONFIG_SYS_BANK2_END		0x00000000
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x00000000
+#define CONFIG_SYS_BANK3_END		0x00000000
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
 
 /*
  * Memory bank enable bitmask, specifying which of the banks defined above
  * are actually present. MSB is for bank #7, LSB is for bank #0.
  */
-#define CFG_BANK_ENABLE		0x01
+#define CONFIG_SYS_BANK_ENABLE		0x01
 
-#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
 					/* see 8240 book for bit definitions	*/
-#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
 					/* currently accessed page in memory	*/
 					/* see 8240 book for details		*/
 
 /* SDRAM 0 - 256MB */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 
 /* PCI memory space */
-#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* Config addrs, etc */
-#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif