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authorKumar Gala <galak@kernel.crashing.org>2008-08-26 23:52:07 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-08-27 11:43:51 -0500
commit6bfa8f723cfd82c55e3ef5620ade396916470a70 (patch)
tree10afcccbcc815720e225b1df18aeebdeb86fcbb6 /include/configs/PM856.h
parentd53bd3e17bd4f460257c19255569ea6dcfaae817 (diff)
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FSL DDR: Convert PM856 to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/PM856.h')
-rw-r--r--include/configs/PM856.h58
1 files changed, 28 insertions, 30 deletions
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index b2cf060..244f09a 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -45,11 +45,6 @@
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
-#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
@@ -97,33 +92,36 @@
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_SPD
+#define CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
-
-#if defined(CONFIG_SPD_EEPROM)
- /*
- * Determine DDR configuration from I2C interface.
- */
- #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */
-
-#else
- /*
- * Manually set up DDR parameters
- */
- #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
- #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
- #define CFG_DDR_CS0_CONFIG 0x80000102
- #define CFG_DDR_TIMING_1 0x47444321
- #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
- #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
- #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
- #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
-#endif
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CFG_DDR_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */
+
+/* Manually set up DDR parameters */
+#define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
+#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
+#define CFG_DDR_CS0_CONFIG 0x80000102
+#define CFG_DDR_TIMING_1 0x47444321
+#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
+#define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
+#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
/*
* SDRAM on the Local Bus