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| author | Wolfgang Denk <wd@denx.de> | 2010-09-28 23:30:47 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-09-28 23:30:47 +0200 |
| commit | 2e6e1772c0e34871769be4aef79748fe3e47d953 (patch) | |
| tree | 00e4e19d7bccd2a1cd5753854ff4c2b8a26bebb0 /include/configs/PLU405.h | |
| parent | 1e4e5ef0469050f014aee1204dae8a9ab6053e49 (diff) | |
| parent | 3df61957938586c512c17e72d83551d190400981 (diff) | |
| download | u-boot-imx-2e6e1772c0e34871769be4aef79748fe3e47d953.zip u-boot-imx-2e6e1772c0e34871769be4aef79748fe3e47d953.tar.gz u-boot-imx-2e6e1772c0e34871769be4aef79748fe3e47d953.tar.bz2 | |
Merge branch 'next' of /home/wd/git/u-boot/next
Conflicts:
include/ppc4xx.h
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include/configs/PLU405.h')
| -rw-r--r-- | include/configs/PLU405.h | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index f917eb5..928ed8e 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -135,9 +135,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -379,12 +384,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x00000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x00000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0x77FE0014 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) |