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author | stroese <stroese> | 2004-12-16 18:05:42 +0000 |
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committer | stroese <stroese> | 2004-12-16 18:05:42 +0000 |
commit | a20b27a36b7b1f593e18b4efd506e5f01a392dc6 (patch) | |
tree | f9dc45c287966bb96c38a8267d07b217727efb3c /include/configs/PLU405.h | |
parent | 44acc8d334a8b9ddb81fc238b094574991f19afa (diff) | |
download | u-boot-imx-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.zip u-boot-imx-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.tar.gz u-boot-imx-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.tar.bz2 |
esd config files updated
Diffstat (limited to 'include/configs/PLU405.h')
-rw-r--r-- | include/configs/PLU405.h | 90 |
1 files changed, 57 insertions, 33 deletions
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 0798af4..73a7885 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -40,33 +40,37 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ -#define CONFIG_SYS_CLK_FREQ 33333334 /* external frequency to pll */ +#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ #define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm ffc00000 ffca0000" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm ffc00000" -#define CONFIG_BOOTCOMMAND "bootm fff00000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#if 0 /* test-only */ +#define CONFIG_NET_MULTI 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY1_ADDR 1 /* PHY address */ +#else #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ +#endif +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_DHCP | \ CFG_CMD_PCI | \ CFG_CMD_IRQ | \ CFG_CMD_IDE | \ + CFG_CMD_FAT | \ CFG_CMD_ELF | \ CFG_CMD_NAND | \ CFG_CMD_DATE | \ @@ -78,6 +82,11 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT + +#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ +#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */ + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -112,6 +121,8 @@ #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ + #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ @@ -131,6 +142,15 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +/* Only interrupt boot if space is pressed */ +/* If a long serial cable is connected but */ +/* other end is dead, garbage will be read */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#undef CONFIG_AUTOBOOT_DELAY_STR +#define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ @@ -169,30 +189,34 @@ #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ +#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ +#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * IDE/ATA stuff |